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a=openpgp-sha256; l=2179; i=cassel@kernel.org; h=from:subject; bh=RjGMQwNSWCZEFnr1KtbG8zsYIWeufEBEVG9ZPVbFPDw=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGDI84/fm7D7B80R4OZ9Gz6Ivf4IrLP2zansvVimoTE07E hRckvuzo5SFQYyLQVZMkcX3h8v+4m73KccV79jAzGFlAhnCwMUpABPpesvwP5mpPNqxjcfh76x5 Rk5V67WjNjOo9R5MEdj3zPH2y1kfGBkZVky5ntBz7FCZ78q1nsvmfZtylOfDmWbuTc+yt0m4fBQ JZgQA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250611_115347_768788_63A7FA08 X-CRM114-Status: GOOD ( 10.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Commit ec9fd499b9c6 ("PCI: dw-rockchip: Don't wait for link since we can detect Link Up") changed so that we no longer call dw_pcie_wait_for_link(), and instead enumerate the bus directly after receiving the Link Up IRQ. This means that there is no longer any delay between link up and the bus getting enumerated. As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link training completes before sending a Configuration Request. Add this delay in the threaded link up IRQ handler in order to satisfy the requirements of the PCIe spec. Laszlo Fiat reported (off-list) that his PLEXTOR PX-256M8PeGN NVMe SSD is no longer functional, and simply reverting commit ec9fd499b9c6 ("PCI: dw-rockchip: Don't wait for link since we can detect Link Up") makes his SSD functional again. Adding the 100 ms delay as required by the spec also makes the SSD functional again. Cc: Laszlo Fiat Fixes: ec9fd499b9c6 ("PCI: dw-rockchip: Don't wait for link since we can detect Link Up") Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 93171a392879..a941a239cbfc 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -459,6 +459,13 @@ static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int irq, void *arg) if (reg & PCIE_RDLH_LINK_UP_CHGED) { if (rockchip_pcie_link_up(pci)) { dev_dbg(dev, "Received Link up event. Starting enumeration!\n"); + /* + * As per PCIe r6.0, sec 6.6.1, a Downstream Port that + * supports Link speeds greater than 5.0 GT/s, software + * must wait a minimum of 100 ms after Link training + * completes before sending a Configuration Request. + */ + msleep(PCIE_T_RRS_READY_MS); /* Rescan the bus to enumerate endpoint devices */ pci_lock_rescan_remove(); pci_rescan_bus(pp->bridge->bus); -- 2.49.0