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Fri, 13 Jun 2025 05:50:53 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v3 6/9] arm64: dts: exynos: ExynosAutov920: add USB and USB HS combo phy nodes Date: Fri, 13 Jun 2025 11:26:10 +0530 Message-Id: <20250613055613.866909-7-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250613055613.866909-1-pritam.sutar@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CMS-MailID: 20250613055056epcas5p29790d8086c89b16441f4b0a9c2a4db33 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250613055056epcas5p29790d8086c89b16441f4b0a9c2a4db33 References: <20250613055613.866909-1-pritam.sutar@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250613_001024_156265_1722C9B9 X-CRM114-Status: GOOD ( 13.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the USB 3.1 DRD controller and USB31DRD HS combo phy nodes for ExynosAutov920 soc. The USB 3.1 DRD controller has the following features: * DWC3 compatible * compliant with both USB device 3.1 and USB device 2.0 standards * compliant with USB host 3.1 and USB host 2.0 standards * supports USB device 3.1 and USB device 2.0 interfaces * supports USB host 3.1 and USB host 2.0 interfaces * full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB device 2.0 interface * super-speed (5 Gbps) mode with USB device 3.1 Gen1 interface * super-speed plus (10 Gbps) mode with USB device 3.1 Gen2 interface * single USB port which can be used for USB 3.1 or USB 2.0 * on-chip USB PHY transceiver * supports up to 16 bi-directional endpoints * compliant with xHCI 1.1 specification Only UTMI+ is supported in this commit, so only UTMI+ PHY interface is specified in "phys" property (index 0) and PIPE3 is omitted (index 1). Signed-off-by: Pritam Manohar Sutar --- .../boot/dts/exynos/exynosautov920-sadk.dts | 12 +++++++ .../arm64/boot/dts/exynos/exynosautov920.dtsi | 36 +++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts index 984e899a2ebf..a21386bd9af3 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts +++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts @@ -88,6 +88,18 @@ &xtcxo { }; /* usb */ +&usbdrd31_hsphy { + status = "okay"; +}; + +&usbdrd31_dwc3 { + dr_mode = "peripheral"; +}; + +&usbdrd31 { + status = "okay"; +}; + &usbdrd20_phy0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index b1a9d1da47f6..4efc005cae80 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1048,6 +1048,17 @@ pinctrl_hsi1: pinctrl@16450000 { interrupts = ; }; + usbdrd31_hsphy: phy@16490000 { + compatible = "samsung,exynosautov920-usbdrd-hsphy"; + reg = <0x16490000 0x0200>; + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>, + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + samsung,pmu-syscon = <&pmu_system_controller>; + status = "disabled"; + }; + usbdrd20_phy0: phy@16500000 { compatible = "samsung,exynosautov920-usbdrd-phy"; reg = <0x16500000 0x0200>; @@ -1081,6 +1092,31 @@ usbdrd20_phy2: phy@16520000 { status = "disabled"; }; + usbdrd31: usb@16600000 { + compatible = "samsung,exynosautov920-dwusb3"; + ranges = <0x0 0x16600000 0x10000>; + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>, + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; + clock-names = "ref", "susp_clk"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + usbdrd31_dwc3: usb@0 { + compatible = "snps,dwc3"; + reg = <0x0 0x10000>; + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>, + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; + clock-names = "ref", "susp_clk"; + interrupts = ; + phys = <&usbdrd31_hsphy 0>; + phy-names = "usb2-phy"; + snps,has-lpm-erratum; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + }; + }; + usbdrd20_0: usb@16700000 { compatible = "samsung,exynosautov920-dwusb3"; ranges = <0x0 0x16700000 0x10000>; -- 2.34.1