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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2365deb2cedsm49932455ad.163.2025.06.15.18.32.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jun 2025 18:32:23 -0700 (PDT) From: Nick Chan Date: Mon, 16 Jun 2025 09:31:52 +0800 Subject: [PATCH RESEND v7 03/21] drivers/perf: apple_m1: Support per-implementation event tables MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250616-apple-cpmu-v7-3-df2778a44d5c@gmail.com> References: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> In-Reply-To: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5769; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=40iBkshuT7rxTV03RILkcUaTWGCgn/IFCgnsDvO8O/4=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoT3QXahV7k8F70XGC8o8Vn+M6DTHkgzxaEC38d y4qcQliEBaJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaE90FwAKCRABygi3psUI JNO5EACIQXBLWxc0imgRlBPChuoQQfWnIM5VL5Ufyz0y4SiKP30ZAmXJdDNOWY/QUO67J7oSfyz JwUqWPx+W/Ms5iMRJdIPs4Aws2kNauZYofpLmodL7tF67e433vcP0zNGxLByA93inHyEvrEPc8A 8owL0c+ZNPSTKSawT+g/55lBdo5KfSxxu84rwHR0EhRiAcf3OZTf8o4CVC47hFEuChiYEGkZy8z Kpd4cEpncwN1JJBdoJBaB5KgfhWjohN1h6uDpNxbK+KI35loLMV8hFT/m3p4ankqa1+8hXnopsi 46Wd6PnIbOb9K57SntS1k/I/l5OgWvnu7ZXbH8IIGWeasGOxgaclXGloGUz8FW6E2L2u02ayWk/ c8z6UchZ4dUpz8hpKnsqshsJPXYUYmNjdBOUR3hfnaOW2q8E3ZxhYtLP0fnZiRykjI+O8WeIZSR AuQdLPdFRZ0/0t++kMAfzZ6mK+ZhjJ25E8+JZtxvcH2tj4kpxVHD78D/NcAYwtFQh++uj7r5GkU c82evqiWwsJkEyNJjVE1w1huqTWTZoyhIACriNJ8nHU37wUofPkC5Vc4OmNAVuXhequ4vFx77E6 PoEUhmCittodPDHqp1ssr10D7IbJtLf9ijvS7pnOzhcKsPhk/Je3Y62beFFOEulB/NhWQEGcXjx UZlF8ntNGkrUqcw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250615_183224_701138_2077B4B7 X-CRM114-Status: GOOD ( 17.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use per-implementation event tables to allow supporting implementations with a different list of events and event affinities. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 65 +++++++++++++++++++++++++---------------- 1 file changed, 40 insertions(+), 25 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index b800da3f7f61ffa972fcab5f24b42127f2c55ac6..c19a433ee6478876e4cf6667d7a85a193b6cb069 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -43,9 +43,6 @@ * moment, we don't really need to distinguish between the two because we * know next to nothing about the events themselves, and we already have * per cpu-type PMU abstractions. - * - * If we eventually find out that the events are different across - * implementations, we'll have to introduce per cpu-type tables. */ enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP = 0x1, @@ -494,11 +491,12 @@ static void m1_pmu_write_counter(struct perf_event *event, u64 value) isb(); } -static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) +static int apple_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event, + const u16 event_affinities[]) { unsigned long evtype = event->hw.config_base & M1_PMU_CFG_EVENT; - unsigned long affinity = m1_pmu_event_affinity[evtype]; + unsigned long affinity = event_affinities[evtype]; int idx; /* @@ -517,6 +515,12 @@ static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, return -EAGAIN; } +static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, m1_pmu_event_affinity); +} + static void m1_pmu_clear_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -544,7 +548,8 @@ static void m1_pmu_stop(struct arm_pmu *cpu_pmu) __m1_pmu_set_mode(PMCR0_IMODE_OFF); } -static int m1_pmu_map_event(struct perf_event *event) +static int apple_pmu_map_event_47(struct perf_event *event, + const unsigned int (*perf_map)[]) { /* * Although the counters are 48bit wide, bit 47 is what @@ -552,18 +557,29 @@ static int m1_pmu_map_event(struct perf_event *event) * being 47bit wide to mimick the behaviour of the ARM PMU. */ event->hw.flags |= ARMPMU_EVT_47BIT; - return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT); + return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); } -static int m2_pmu_map_event(struct perf_event *event) +static int apple_pmu_map_event_63(struct perf_event *event, + const unsigned int (*perf_map)[]) { /* - * Same deal as the above, except that M2 has 64bit counters. + * Same deal as the above, except with 64bit counters. * Which, as far as we're concerned, actually means 63 bits. * Yes, this is getting awkward. */ event->hw.flags |= ARMPMU_EVT_63BIT; - return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT); + return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); +} + +static int m1_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_47(event, &m1_pmu_perf_map); +} + +static int m2_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_63(event, &m1_pmu_perf_map); } static int m1_pmu_map_pmuv3_event(unsigned int eventsel) @@ -624,25 +640,16 @@ static int m1_pmu_set_event_filter(struct hw_perf_event *event, return 0; } -static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 flags) +static int apple_pmu_init(struct arm_pmu *cpu_pmu) { cpu_pmu->handle_irq = m1_pmu_handle_irq; cpu_pmu->enable = m1_pmu_enable_event; cpu_pmu->disable = m1_pmu_disable_event; cpu_pmu->read_counter = m1_pmu_read_counter; cpu_pmu->write_counter = m1_pmu_write_counter; - cpu_pmu->get_event_idx = m1_pmu_get_event_idx; cpu_pmu->clear_event_idx = m1_pmu_clear_event_idx; cpu_pmu->start = m1_pmu_start; cpu_pmu->stop = m1_pmu_stop; - - if (flags & ARMPMU_EVT_47BIT) - cpu_pmu->map_event = m1_pmu_map_event; - else if (flags & ARMPMU_EVT_63BIT) - cpu_pmu->map_event = m2_pmu_map_event; - else - return WARN_ON(-EINVAL); - cpu_pmu->reset = m1_pmu_reset; cpu_pmu->set_event_filter = m1_pmu_set_event_filter; @@ -661,25 +668,33 @@ static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 flags) static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_icestorm_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_47BIT); + cpu_pmu->get_event_idx = m1_pmu_get_event_idx; + cpu_pmu->map_event = m1_pmu_map_event; + return apple_pmu_init(cpu_pmu); } static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_firestorm_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_47BIT); + cpu_pmu->get_event_idx = m1_pmu_get_event_idx; + cpu_pmu->map_event = m1_pmu_map_event; + return apple_pmu_init(cpu_pmu); } static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_avalanche_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_63BIT); + cpu_pmu->get_event_idx = m1_pmu_get_event_idx; + cpu_pmu->map_event = m2_pmu_map_event; + return apple_pmu_init(cpu_pmu); } static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_blizzard_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_63BIT); + cpu_pmu->get_event_idx = m1_pmu_get_event_idx; + cpu_pmu->map_event = m2_pmu_map_event; + return apple_pmu_init(cpu_pmu); } static const struct of_device_id m1_pmu_of_device_ids[] = { -- 2.49.0