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From: Sean Anderson <sean.anderson@linux.dev>
To: Mark Brown <broonie@kernel.org>,
	Michal Simek <michal.simek@amd.com>,
	linux-spi@vger.kernel.org
Cc: Jinjie Ruan <ruanjinjie@huawei.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	David Lechner <dlechner@baylibre.com>,
	Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>,
	Sean Anderson <sean.anderson@linux.dev>
Subject: [PATCH v2 1/9] dt-bindings: spi: Add spi-buses property
Date: Mon, 16 Jun 2025 18:00:46 -0400	[thread overview]
Message-ID: <20250616220054.3968946-2-sean.anderson@linux.dev> (raw)
In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev>

From: David Lechner <dlechner@baylibre.com>

Add a spi-buses property to the spi-peripheral-props binding to allow
specifying the SPI bus or buses that a peripheral is connected to in
cases where the SPI controller has more than one physical SPI bus.

Signed-off-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
---

Changes in v2:
- New

 .../devicetree/bindings/spi/spi-peripheral-props.yaml  | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
index 8fc17e16efb2..cfdb55071a08 100644
--- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
@@ -89,6 +89,16 @@ properties:
     description:
       Delay, in microseconds, after a write transfer.
 
+  spi-buses:
+    description:
+      Array of bus numbers that describes which SPI buses of the controller are
+      connected to the peripheral. This only applies to peripherals connected
+      to specialized SPI controllers that have multiple SPI buses on a single
+      controller.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    default: [0]
+
   stacked-memories:
     description: Several SPI memories can be wired in stacked mode.
       This basically means that either a device features several chip
-- 
2.35.1.1320.gc452695387.dirty



  reply	other threads:[~2025-06-16 22:20 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-16 22:00 [PATCH v2 0/9] spi: zynqmp-gqspi: Support multiple buses and add GPIO support Sean Anderson
2025-06-16 22:00 ` Sean Anderson [this message]
2025-06-17  6:05   ` [PATCH v2 1/9] dt-bindings: spi: Add spi-buses property Krzysztof Kozlowski
2025-08-14 20:55   ` David Lechner
2025-08-14 21:15     ` Sean Anderson
2025-08-14 21:17       ` David Lechner
2025-08-14 21:34         ` Sean Anderson
2025-08-14 22:08       ` Mark Brown
2025-08-15 15:49   ` David Lechner
2025-08-18  8:28     ` Miquel Raynal
2025-08-18 14:55       ` Sean Anderson
2025-08-18 15:22       ` David Lechner
2025-08-18 14:56     ` Sean Anderson
2025-08-18 15:26       ` David Lechner
2025-06-16 22:00 ` [PATCH v2 2/9] dt-bindings: spi: zynqmp-qspi: Add example dual upper/lower bus Sean Anderson
2025-06-17  1:59   ` Rob Herring (Arm)
2025-06-18 18:27   ` David Lechner
2025-06-19 16:20     ` Sean Anderson
2025-06-19 16:29       ` David Lechner
2025-06-16 22:00 ` [PATCH v2 3/9] spi: Support multi-bus controllers Sean Anderson
2025-06-16 22:00 ` [PATCH v2 4/9] spi: Add flag to determine default bus Sean Anderson
2025-06-16 22:00 ` [PATCH v2 5/9] spi: zynqmp-gqspi: Support multiple buses Sean Anderson
2025-06-16 23:10   ` David Lechner
2025-06-17 13:21   ` kernel test robot
2025-06-16 22:00 ` [PATCH v2 6/9] spi: zynqmp-gqspi: Pass speed directly to config_op Sean Anderson
2025-06-16 22:00 ` [PATCH v2 7/9] spi: zynqmp-gqspi: Configure SPI mode dynamically Sean Anderson
2025-06-16 22:00 ` [PATCH v2 8/9] spi: zynqmp-gqspi: Support GPIO chip selects Sean Anderson
2025-06-16 22:00 ` [PATCH v2 9/9] ARM64: xilinx: zynqmp: Add spi-buses property Sean Anderson
2025-06-17  6:07   ` Krzysztof Kozlowski

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