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From: Sean Anderson <sean.anderson@linux.dev>
To: Mark Brown <broonie@kernel.org>,
	Michal Simek <michal.simek@amd.com>,
	linux-spi@vger.kernel.org
Cc: Jinjie Ruan <ruanjinjie@huawei.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	David Lechner <dlechner@baylibre.com>,
	Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>,
	Sean Anderson <sean.anderson@linux.dev>
Subject: [PATCH v2 5/9] spi: zynqmp-gqspi: Support multiple buses
Date: Mon, 16 Jun 2025 18:00:50 -0400	[thread overview]
Message-ID: <20250616220054.3968946-6-sean.anderson@linux.dev> (raw)
In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev>

Currently, selection of the upper/lower buses is determined by the
chipselect. Decouple this by allowing explicit bus selection through the
spi-buses property.

Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
---

Changes in v2:
- New

 drivers/spi/spi-zynqmp-gqspi.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c
index 595b6dc10845..add5eea12153 100644
--- a/drivers/spi/spi-zynqmp-gqspi.c
+++ b/drivers/spi/spi-zynqmp-gqspi.c
@@ -465,13 +465,13 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
 	genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
 
 	if (!is_high) {
-		if (!spi_get_chipselect(qspi, 0)) {
-			xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
+		xqspi->genfifobus =
+			FIELD_PREP(GQSPI_GENFIFO_BUS_MASK, qspi->buses);
+		if (!spi_get_chipselect(qspi, 0))
 			xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;
-		} else {
-			xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
+		else
 			xqspi->genfifocs = GQSPI_GENFIFO_CS_UPPER;
-		}
+
 		genfifoentry |= xqspi->genfifobus;
 		genfifoentry |= xqspi->genfifocs;
 		genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
@@ -1316,6 +1316,8 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
 		ctlr->num_chipselect = num_cs;
 	}
 
+	ctlr->num_buses = 2;
+	ctlr->flags = SPI_CONTROLLER_DEFAULT_BUS_IS_CS;
 	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
 	ctlr->mem_ops = &zynqmp_qspi_mem_ops;
 	ctlr->mem_caps = &zynqmp_qspi_mem_caps;
-- 
2.35.1.1320.gc452695387.dirty



  parent reply	other threads:[~2025-06-16 22:13 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-16 22:00 [PATCH v2 0/9] spi: zynqmp-gqspi: Support multiple buses and add GPIO support Sean Anderson
2025-06-16 22:00 ` [PATCH v2 1/9] dt-bindings: spi: Add spi-buses property Sean Anderson
2025-06-17  6:05   ` Krzysztof Kozlowski
2025-08-14 20:55   ` David Lechner
2025-08-14 21:15     ` Sean Anderson
2025-08-14 21:17       ` David Lechner
2025-08-14 21:34         ` Sean Anderson
2025-08-14 22:08       ` Mark Brown
2025-08-15 15:49   ` David Lechner
2025-08-18  8:28     ` Miquel Raynal
2025-08-18 14:55       ` Sean Anderson
2025-08-18 15:22       ` David Lechner
2025-08-18 14:56     ` Sean Anderson
2025-08-18 15:26       ` David Lechner
2025-06-16 22:00 ` [PATCH v2 2/9] dt-bindings: spi: zynqmp-qspi: Add example dual upper/lower bus Sean Anderson
2025-06-17  1:59   ` Rob Herring (Arm)
2025-06-18 18:27   ` David Lechner
2025-06-19 16:20     ` Sean Anderson
2025-06-19 16:29       ` David Lechner
2025-06-16 22:00 ` [PATCH v2 3/9] spi: Support multi-bus controllers Sean Anderson
2025-06-16 22:00 ` [PATCH v2 4/9] spi: Add flag to determine default bus Sean Anderson
2025-06-16 22:00 ` Sean Anderson [this message]
2025-06-16 23:10   ` [PATCH v2 5/9] spi: zynqmp-gqspi: Support multiple buses David Lechner
2025-06-17 13:21   ` kernel test robot
2025-06-16 22:00 ` [PATCH v2 6/9] spi: zynqmp-gqspi: Pass speed directly to config_op Sean Anderson
2025-06-16 22:00 ` [PATCH v2 7/9] spi: zynqmp-gqspi: Configure SPI mode dynamically Sean Anderson
2025-06-16 22:00 ` [PATCH v2 8/9] spi: zynqmp-gqspi: Support GPIO chip selects Sean Anderson
2025-06-16 22:00 ` [PATCH v2 9/9] ARM64: xilinx: zynqmp: Add spi-buses property Sean Anderson
2025-06-17  6:07   ` Krzysztof Kozlowski

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