From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8882EC71157 for ; Wed, 18 Jun 2025 11:36:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Qu2L3R5zU3pfooW941saPxIblz4kIELfHaA2n8pmdWY=; b=uj1TpmXBr3IWFsF98P2qxIXBz8 zjQi9dy/OVQsQX/95iOqk8RSVBWA19d308zpOYtGV08XvaainbXPs0YeUcA9TLAO092YsmCTjvWIc XYnPCBTQzMTpIhyAo9OvTOe0MGJgsgImckZ8FSQFL42lW3JkSt75nfO37XppzgR6fBK3HhkzA/hhs k3hUzJmRKFkukHluN5Jf4Oe+GJlqDmHCaLgykz1dQ0vtaY+y3PxCgKLbkXoXy/mdlTGnkKlDMlEmy tXhCr7mrwc3JuEe9aXCNtnzMrUQ9qmhSgGVNW9JvVkaJ2zUoFUtUqGJXQWf6tcYxh+HubJfxa4a9f LHkEuymg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uRr5y-00000009xsr-2XhW; Wed, 18 Jun 2025 11:36:46 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uRpt1-00000009kYB-3Ebo for linux-arm-kernel@lists.infradead.org; Wed, 18 Jun 2025 10:19:20 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id B41385C6614; Wed, 18 Jun 2025 10:17:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1BF44C4CEED; Wed, 18 Jun 2025 10:19:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750241959; bh=/dE8LD/ePWA/0RVJBLeEqlL5qzeRTK7k8l1BILw0Xkg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=HtoE2TO6nsiem4sAbZcXTKDCGXCBgTjpiHmkRiYS9OiD4ThIoIAuhHdMM7neLqGng /WRXK9uIew4Ok+5QERMRAiSQySJKufdEQKEHFYcbL6I8AXuujy8AzkUgo5OkKkazCd URTPKvhJfXUtdtI6xLmhfYIQ/vfeKZspkFqmOMULz4NnBnpxQA/ABdTOjdpM7V6l1u h7NoQITY3WAX9GW5NilbFJRfK/6xxvnEVdrUVWDM5qG7vjMxIg9njmHUnATKf6+uTg p4lrzfehi7dnpyv+gkmDwY32TmztOcofMZr9GqpvCqSg5d+o4N4xhwg0R9M4nQK0eI Q2eZbJ0scdyWg== From: Lorenzo Pieralisi Date: Wed, 18 Jun 2025 12:17:32 +0200 Subject: [PATCH v5 17/27] arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250618-gicv5-host-v5-17-d9e622ac5539@kernel.org> References: <20250618-gicv5-host-v5-0-d9e622ac5539@kernel.org> In-Reply-To: <20250618-gicv5-host-v5-0-d9e622ac5539@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Jonathan Cameron , Timothy Hayes , Bjorn Helgaas , "Liam R. Howlett" , Peter Maydell , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.15-dev-6f78e X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250618_031919_856670_CA5365DD X-CRM114-Status: GOOD ( 10.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Implement the GCIE capability as a strict boot cpu capability to detect whether architectural GICv5 support is available in HW. Plug it in with a naming consistent with the existing GICv3 CPU interface capability. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/kernel/cpufeature.c | 7 +++++++ arch/arm64/tools/cpucaps | 1 + 2 files changed, 8 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 42ba76b6c8cd..2fa26129762c 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -3061,6 +3061,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_pmuv3, }, #endif + { + .desc = "GICv5 CPU interface", + .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, + .capability = ARM64_HAS_GICV5_CPUIF, + .matches = has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) + }, {}, }; diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index a7a4d9e6e12e..8665e4cfbeab 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -36,6 +36,7 @@ HAS_GENERIC_AUTH_ARCH_QARMA3 HAS_GENERIC_AUTH_ARCH_QARMA5 HAS_GENERIC_AUTH_IMP_DEF HAS_GICV3_CPUIF +HAS_GICV5_CPUIF HAS_GIC_PRIO_MASKING HAS_GIC_PRIO_RELAXED_SYNC HAS_HCR_NV1 -- 2.48.0