[PATCHv4 0/6] Add support for AM62D2 SoC and EVM

[PATCHv4 0/6] Add support for AM62D2 SoC and EVM

[Paresh Bhagat]

This patch series adds support for the AM62D SoC and its evaluation
module (EVM) board, enable eMMC and firmware-name update for
AM62D2-EVM board.

The AM62D SoC is a high-performance Digital Signal Processing (DSP)
device with a quad-core Cortex-A53 cluster, dual Cortex-R5F cores,
and a Cx7 DSP core with Matrix Multiplication Accelerator (MMA).
It features a range of peripherals, including multichannel audio
serial ports, Ethernet, UARTs, SPI, I2C, USB, and more.

The EVM board is a low-cost, expandable platform designed for the AM62D2
SoC, having 4GB LPDDR4 RAM, Gigabit Ethernet expansion connectors, audio
jacks, USB ports, and more.

This SoC is part K3 AM62x family, which includes the AM62A and AM62P
variants. While the AM62A and AM62D are largely similar, the AM62D is
specifically targeted for general-purpose DSP applications, whereas the
AM62A focuses on edge AI workloads. A key distinction is that the AM62D
does not include multimedia components such as the video encoder/decoder,
MJPEG encoder, Vision Processing Accelerator (VPAC) for image signal
processing, or the display subsystem. Additionally, the AM62D has a
different pin configuration compared to the AM62A, which impacts embedded
software development.

This patch series includes updates to the dts and dtsi files, device tree
bindings, and pin control header files to support the AM62D SoC and EVM
board.

Bootlog-

SD Card
https://gist.github.com/paresh-bhagat12/1757cc54a39f1baf883341af2a383db6

eMMC
https://gist.github.com/paresh-bhagat12/36c756422ff71fa9568c45e9b44332f0

Tech Ref Manual-https://www.ti.com/lit/pdf/sprujd4
Schematics Link-https://www.ti.com/lit/zip/sprcal5

Change Log:
V3 -> V4:
	- Added bootph-all property at source nodes.
	- Reuse dtsi files of am62a (instead of common files).
	- Added eMMC support.
	- Updated firmware name for am62d.

V2 -> V3:
	- Added bootph-all property to essential device nodes.
	- Updated reserved memory for ATF.
	- Introduce common dtsi files for AM62A and AM62D.

V1 -> V2: Fixed indentation and build errors.

Paresh Bhagat (6):
  arm64: dts: ti: Add bootph property to nodes at source for am62a
  dt-bindings: arm: ti: Add bindings for AM62D2 SoC
  arm64: dts: ti: Add pinctrl entries for AM62D2 family of SoCs
  arm64: dts: ti: Add support for AM62D2-EVM
  arm64: dts: ti: Update firmware-name for IPC
  arm64: dts: ti: Add eMMC support for AM62D

 .../devicetree/bindings/arm/ti/k3.yaml        |   6 +
 arch/arm64/boot/dts/ti/Makefile               |   3 +
 arch/arm64/boot/dts/ti/k3-am62a-main.dtsi     |  15 +
 arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi      |   1 +
 arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi   |   3 +
 arch/arm64/boot/dts/ti/k3-am62a.dtsi          |   3 +
 arch/arm64/boot/dts/ti/k3-am62d2-evm.dts      | 590 ++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-pinctrl.h           |   3 +
 8 files changed, 624 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62d2-evm.dts

-- 
2.34.1

[PATCHv4 1/6] arm64: dts: ti: Add bootph property to nodes at source for am62a

[Paresh Bhagat]

Add bootph property directly into the original definitions of relevant
nodes (e.g., power domains, USB controllers, and other peripherals)
within their respective DTSI files (ex. main, mcu, and wakeup)i for
am62a.

By defining bootph in the nodes source definitions instead of appending
it later in final DTS files, this change ensures that the property is
inherently present wherever the nodes are reused across derived device
trees.

Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am62a-main.dtsi   | 15 +++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi    |  1 +
 arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi |  3 +++
 arch/arm64/boot/dts/ti/k3-am62a.dtsi        |  3 +++
 4 files changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
index 63e097ddf988..1b7fe4487475 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
@@ -51,6 +51,7 @@ phy_gmii_sel: phy@4044 {
 			compatible = "ti,am654-phy-gmii-sel";
 			reg = <0x4044 0x8>;
 			#phy-cells = <1>;
+			bootph-all;
 		};
 
 		epwm_tbclk: clock-controller@4130 {
@@ -84,6 +85,7 @@ dmss: bus@48000000 {
 		#size-cells = <2>;
 		dma-ranges;
 		ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>;
+		bootph-all;
 
 		ti,sci-dev-id = <25>;
 
@@ -96,6 +98,7 @@ secure_proxy_main: mailbox@4d000000 {
 			#mbox-cells = <1>;
 			interrupt-names = "rx_012";
 			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			bootph-all;
 		};
 
 		inta_main_dmss: interrupt-controller@48000000 {
@@ -131,6 +134,7 @@ main_bcdma: dma-controller@485c0100 {
 			ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
 			ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
 			ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
+			bootph-all;
 		};
 
 		main_pktdma: dma-controller@485c0000 {
@@ -167,6 +171,7 @@ main_pktdma: dma-controller@485c0000 {
 						<0x2c>, /* FLOW_CPSW_RX_CHAN */
 						<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
 						<0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
+			bootph-all;
 		};
 	};
 
@@ -216,20 +221,24 @@ dmsc: system-controller@44043000 {
 		mbox-names = "rx", "tx";
 		mboxes = <&secure_proxy_main 12>,
 			 <&secure_proxy_main 13>;
+		bootph-all;
 
 		k3_pds: power-controller {
 			compatible = "ti,sci-pm-domain";
 			#power-domain-cells = <2>;
+			bootph-all;
 		};
 
 		k3_clks: clock-controller {
 			compatible = "ti,k2g-sci-clk";
 			#clock-cells = <2>;
+			bootph-all;
 		};
 
 		k3_reset: reset-controller {
 			compatible = "ti,sci-reset";
 			#reset-cells = <2>;
+			bootph-all;
 		};
 	};
 
@@ -254,6 +263,7 @@ secure_proxy_sa3: mailbox@43600000 {
 		 * firmware on non-MPU processors
 		 */
 		status = "disabled";
+		bootph-all;
 	};
 
 	main_pmx0: pinctrl@f4000 {
@@ -262,6 +272,7 @@ main_pmx0: pinctrl@f4000 {
 		#pinctrl-cells = <1>;
 		pinctrl-single,register-width = <32>;
 		pinctrl-single,function-mask = <0xffffffff>;
+		bootph-all;
 	};
 
 	main_esm: esm@420000 {
@@ -282,6 +293,7 @@ main_timer0: timer@2400000 {
 		assigned-clock-parents = <&k3_clks 36 3>;
 		power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
 		ti,timer-pwm;
+		bootph-all;
 	};
 
 	main_timer1: timer@2410000 {
@@ -653,6 +665,7 @@ usb0: usb@31000000 {
 			dr_mode = "otg";
 			snps,usb2-gadget-lpm-disable;
 			snps,usb2-lpm-disable;
+			bootph-all;
 		};
 	};
 
@@ -745,6 +758,7 @@ cpsw_port1: port@1 {
 				phys = <&phy_gmii_sel 1>;
 				mac-address = [00 00 00 00 00 00];
 				ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
+				bootph-all;
 			};
 
 			cpsw_port2: port@2 {
@@ -764,6 +778,7 @@ cpsw3g_mdio: mdio@f00 {
 			clocks = <&k3_clks 13 0>;
 			clock-names = "fck";
 			bus_freq = <1000000>;
+			bootph-all;
 		};
 
 		cpts@3d000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi
index ee961ced7208..df4aa131097f 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi
@@ -12,6 +12,7 @@ mcu_pmx0: pinctrl@4084000 {
 		#pinctrl-cells = <1>;
 		pinctrl-single,register-width = <32>;
 		pinctrl-single,function-mask = <0xffffffff>;
+		bootph-all;
 	};
 
 	mcu_esm: esm@4100000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
index 259ae6ebbfb5..86aae252385c 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
@@ -13,10 +13,12 @@ wkup_conf: bus@43000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0x00 0x00 0x43000000 0x20000>;
+		bootph-all;
 
 		chipid: chipid@14 {
 			compatible = "ti,am654-chipid";
 			reg = <0x14 0x4>;
+			bootph-all;
 		};
 
 		opp_efuse_table: syscon@18 {
@@ -67,6 +69,7 @@ wkup_uart0: serial@0 {
 			reg = <0 0x100>;
 			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
+			bootph-pre-ram;
 	       };
 	};
 
diff --git a/arch/arm64/boot/dts/ti/k3-am62a.dtsi b/arch/arm64/boot/dts/ti/k3-am62a.dtsi
index 4d79b3e9486a..54eab2c93eff 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a.dtsi
@@ -50,6 +50,7 @@ cbass_main: bus@f0000 {
 		compatible = "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <2>;
+		bootph-all;
 
 		ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
 			 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
@@ -104,6 +105,7 @@ cbass_mcu: bus@4000000 {
 				 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
 				 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
 				 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
+			bootph-all;
 		};
 
 		cbass_wakeup: bus@b00000 {
@@ -115,6 +117,7 @@ cbass_wakeup: bus@b00000 {
 				 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
 				 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
 				 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
+			bootph-all;
 		};
 	};
 
-- 
2.34.1

[PATCHv4 2/6] dt-bindings: arm: ti: Add bindings for AM62D2 SoC

[Paresh Bhagat]

The AM62D2 SoC belongs to the K3 Multicore SoC architecture with DSP core
targeted for applications needing high-performance Digital Signal
Processing. It is used in applications like automotive audio systems,
professional sound equipment, radar and radio for aerospace, sonar in
marine devices, and ultrasound in medical imaging. It also supports
precise signal analysis in test and measurement tools.

Some highlights of AM62D2 SoC are:

* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single
  core variants are provided in the same package to allow HW compatible
  designs.
* One Device manager Cortex-R5F for system power and resource management,
  and one Cortex-R5F for Functional Safety or general-purpose usage.
* DSP with Matrix Multiplication Accelerator(MMA) (up to 2 TOPS) based on
  single core C7x.
* 3x Multichannel Audio Serial Ports (McASP) Up to 4/6/16 Serial Data Pins
  which can Transmit and Receive Clocks up to 50MHz, with multi-channel I2S
  and TDM Audio inputs and outputs.
* Integrated Giga-bit Ethernet switch supporting up to a total of two
  external ports with TSN capable to enable audio networking features such
  as, Ethernet Audio Video Bridging (eAVB) and Dante.
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, OSPI memory
  controller, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other
  peripherals.
* Dedicated Centralized Hardware Security Module with support for secure
  boot, debug security and crypto acceleration and trusted execution
  environment.
* One 32 bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
* Low power mode support: Partial IO support for CAN/GPIO/UART wakeup.

This SoC is of part K3 AM62x family, which includes the AM62A and AM62P
variants. While the AM62A and AM62D are largely similar, the AM62D is
specifically targeted for general-purpose DSP applications, whereas the
AM62A focuses on edge AI workloads. A key distinction is that the AM62D
does not include multimedia components such as the video encoder/decoder,
MJPEG encoder, Vision Processing Accelerator (VPAC) for image signal
processing, or the display subsystem. Additionally, the AM62D has a
different pin configuration compared to the AM62A, which impacts
embedded software development.

This adds dt bindings for TI's AM62D2 family of devices.

More details about the SoCs can be found in the Technical Reference Manual:
https://www.ti.com/lit/pdf/sprujd4

Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
---
 Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
index bf6003d8fb76..e80c653fa438 100644
--- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
+++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
@@ -25,6 +25,12 @@ properties:
               - ti,am62a7-sk
           - const: ti,am62a7
 
+      - description: K3 AM62D2 SoC and Boards
+        items:
+          - enum:
+              - ti,am62d2-evm
+          - const: ti,am62d2
+
       - description: K3 AM62A7 SoC PHYTEC phyBOARD-Lyra
         items:
           - const: phytec,am62a7-phyboard-lyra-rdk
-- 
2.34.1

[PATCHv4 3/6] arm64: dts: ti: Add pinctrl entries for AM62D2 family of SoCs

[Paresh Bhagat]

Update k3-pinctrl file to include pin definitions for AM62D2 family of
SoCs.

Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
---
 arch/arm64/boot/dts/ti/k3-pinctrl.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h
index cac7cccc1112..0cf57179c974 100644
--- a/arch/arm64/boot/dts/ti/k3-pinctrl.h
+++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h
@@ -63,6 +63,9 @@
 #define AM62AX_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
 #define AM62AX_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
 
+#define AM62DX_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM62DX_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
+
 #define AM62PX_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
 #define AM62PX_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
 
-- 
2.34.1

[PATCHv4 4/6] arm64: dts: ti: Add support for AM62D2-EVM

[Paresh Bhagat]

AM62D-EVM evaluation module (EVM) is a low-cost expandable platform board
designed for AM62D2 SoC from TI. It supports the following interfaces:

* 4 GB LPDDR4 RAM
* x2 Gigabit Ethernet expansion connectors
* x4 3.5mm TRS Audio Jack Line In
* x4 3.5mm TRS Audio Jack Line Out
* x2 Audio expansion connectors
* x1 Type-A USB 2.0, x1 Type-C dual-role device (DRD) USB 2.0
* x1 UHS-1 capable micro SD card slot
* 32 GB eMMC Flash
* 512 Mb OSPI NOR flash
* x4 UARTs via USB 2.0-B
* XDS110 for onboard JTAG debug using USB
* Temperature sensors, user push buttons and LEDs

Although AM62D2 and AM62A7 differ in peripheral capabilities example
multimedia, VPAC, and display subsystems, the core architecture remains
same. To reduce duplication, AM62D support reuses the AM62A dtsi and the
necessary overrides will be handled in the board specific DTS. Add
basic support for AM62D2-EVM.

Schematics Link - https://www.ti.com/lit/zip/sprcal5

Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 arch/arm64/boot/dts/ti/Makefile          |   3 +
 arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 561 +++++++++++++++++++++++
 2 files changed, 564 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62d2-evm.dts

diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index c6171de9fe88..3da3a1d1dc33 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -33,6 +33,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-pocketbeagle2.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am62a7-phyboard-lyra-rdk.dtb
 
+# Boards with AM62Dx SoC
+dtb-$(CONFIG_ARCH_K3) += k3-am62d2-evm.dtb
+
 # Boards with AM62Px SoC
 dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dahlia.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
new file mode 100644
index 000000000000..8fde89ecba67
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
@@ -0,0 +1,561 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * AM62D2 EVM: https://www.ti.com/lit/zip/sprcal5
+ *
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include "k3-am62a7.dtsi"
+
+/ {
+	compatible = "ti,am62d2-evm", "ti,am62d2";
+	model = "Texas Instruments AM62D2 EVM";
+
+	aliases {
+		serial0 = &wkup_uart0;
+		serial1 = &mcu_uart0;
+		serial2 = &main_uart0;
+		mmc1 = &sdhci1;
+		rtc0 = &wkup_rtc0;
+		ethernet0 = &cpsw_port1;
+		ethernet1 = &cpsw_port2;
+	};
+
+	chosen {
+		stdout-path = &main_uart0;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 4G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+		      <0x00000008 0x80000000 0x00000000 0x80000000>;
+		bootph-all;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		bootph-pre-ram;
+
+		/* global cma region */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x00 0x2000000>;
+			alloc-ranges = <0x00 0xc0000000 0x00 0x2000000>;
+			linux,cma-default;
+		};
+
+		secure_tfa_ddr: tfa@80000000 {
+			reg = <0x00 0x80000000 0x00 0x80000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		c7x_0_dma_memory_region: c7x-dma-memory@99800000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x99800000 0x00 0x100000>;
+			no-map;
+		};
+
+		c7x_0_memory_region: c7x-memory@99900000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x99900000 0x00 0xf00000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x9b800000 0x00 0x100000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x9b900000 0x00 0xf00000>;
+			no-map;
+		};
+
+		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x9c800000 0x00 0x100000>;
+			no-map;
+		};
+
+		wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x9c900000 0x00 0xf00000>;
+			no-map;
+			bootph-pre-ram;
+		};
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+			alignment = <0x1000>;
+			no-map;
+		};
+	};
+
+	opp-table {
+		/* Requires VDD_CORE at 0v85 */
+		opp-1400000000 {
+			opp-hz = /bits/ 64 <1400000000>;
+			opp-supported-hw = <0x01 0x0004>;
+			clock-latency-ns = <6000000>;
+		};
+	};
+
+	vout_pd: regulator-1 {
+		/* TPS65988 PD CONTROLLER OUTPUT */
+		compatible = "regulator-fixed";
+		regulator-name = "vout_pd";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+		bootph-all;
+	};
+
+	vmain_pd: load-switch {
+		/* Output of TPS22811 */
+		compatible = "regulator-fixed";
+		regulator-name = "vmain_pd";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vout_pd>;
+		regulator-always-on;
+		regulator-boot-on;
+		bootph-all;
+	};
+
+	vcc_5v0: regulator-2 {
+		/* Output of TPS630702RNMR */
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vmain_pd>;
+		regulator-always-on;
+		regulator-boot-on;
+		bootph-all;
+	};
+
+	vdd_mmc1: regulator-3 {
+		/* TPS22918DBVR */
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_mmc1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		enable-active-high;
+		gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
+		bootph-all;
+	};
+
+	vddshv_sdio: regulator-4 {
+		compatible = "regulator-gpio";
+		regulator-name = "vddshv_sdio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&vddshv_sdio_pins_default>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		gpios = <&main_gpio1 31 GPIO_ACTIVE_HIGH>;
+		states = <1800000 0x0>,
+			 <3300000 0x1>;
+		bootph-all;
+	};
+};
+
+&mcu_pmx0 {
+	wkup_uart0_pins_default: wkup-uart0-default-pins {
+		pinctrl-single,pins = <
+			AM62DX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */
+			AM62DX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */
+			AM62DX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */
+			AM62DX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */
+		>;
+		bootph-all;
+	};
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&wkup_uart0_pins_default>;
+	status = "reserved";
+	bootph-all;
+};
+
+&main_pmx0 {
+	main_uart0_pins_default: main-uart0-default-pins {
+		pinctrl-single,pins = <
+			AM62DX_IOPAD(0x01c8, PIN_INPUT, 0) /* (E14) UART0_RXD */
+			AM62DX_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */
+		>;
+		bootph-all;
+	};
+
+	main_i2c0_pins_default: main-i2c0-default-pins {
+		pinctrl-single,pins = <
+			AM62DX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D17) I2C0_SCL */
+			AM62DX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (E16) I2C0_SDA */
+		>;
+		bootph-all;
+	};
+
+	main_i2c1_pins_default: main-i2c1-default-pins {
+		pinctrl-single,pins = <
+			AM62DX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C17) I2C1_SCL */
+			AM62DX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (E17) I2C1_SDA */
+		>;
+		bootph-all;
+	};
+
+	main_i2c2_pins_default: main-i2c2-default-pins {
+		pinctrl-single,pins = <
+			AM62DX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (M22) GPMC0_CSn2.I2C2_SCL */
+			AM62DX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (M20) GPMC0_CSn3.I2C2_SDA */
+		>;
+	};
+
+	main_mmc1_pins_default: main-mmc1-default-pins {
+		pinctrl-single,pins = <
+			AM62DX_IOPAD(0x023c, PIN_INPUT, 0) /* (C21) MMC1_CMD */
+			AM62DX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (E22) MMC1_CLK */
+			AM62DX_IOPAD(0x0230, PIN_INPUT, 0) /* (B22) MMC1_DAT0 */
+			AM62DX_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (D21) MMC1_DAT1 */
+			AM62DX_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (C22) MMC1_DAT2 */
+			AM62DX_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */
+			AM62DX_IOPAD(0x0240, PIN_INPUT, 0) /* (E18) MMC1_SDCD */
+			AM62DX_IOPAD(0x0244, PIN_INPUT, 0) /* (D18) MMC1_SDWP */
+		>;
+		bootph-all;
+	};
+
+	main_mdio0_pins_default: main-mdio0-default-pins {
+		pinctrl-single,pins = <
+			AM62DX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
+			AM62DX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
+		>;
+		bootph-all;
+	};
+
+	main_rgmii1_pins_default: main-rgmii1-default-pins {
+		pinctrl-single,pins = <
+			AM62DX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */
+			AM62DX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */
+			AM62DX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */
+			AM62DX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */
+			AM62DX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */
+			AM62DX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */
+			AM62DX_IOPAD(0x134, PIN_INPUT, 0) /* (Y17) RGMII1_TD0 */
+			AM62DX_IOPAD(0x138, PIN_INPUT, 0) /* (V16) RGMII1_TD1 */
+			AM62DX_IOPAD(0x13c, PIN_INPUT, 0) /* (Y16) RGMII1_TD2 */
+			AM62DX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 */
+			AM62DX_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AB17) RGMII1_TXC */
+			AM62DX_IOPAD(0x012c, PIN_OUTPUT, 0) /* (W16) RGMII1_TX_CTL */
+		>;
+		bootph-all;
+	};
+
+	main_rgmii2_pins_default: main-rgmii2-default-pins {
+		pinctrl-single,pins = <
+			AM62DX_IOPAD(0x0184, PIN_INPUT, 0) /* (AA21) RGMII2_RD0 */
+			AM62DX_IOPAD(0x0188, PIN_INPUT, 0) /* (Y20) RGMII2_RD1 */
+			AM62DX_IOPAD(0x018c, PIN_INPUT, 0) /* (AB21) RGMII2_RD2 */
+			AM62DX_IOPAD(0x0190, PIN_INPUT, 0) /* (AB20) RGMII2_RD3 */
+			AM62DX_IOPAD(0x0180, PIN_INPUT, 0) /* (AA20) RGMII2_RXC */
+			AM62DX_IOPAD(0x017c, PIN_INPUT, 0) /* (W18) RGMII2_RX_CTL */
+			AM62DX_IOPAD(0x016c, PIN_INPUT, 0) /* (AA19) RGMII2_TD0 */
+			AM62DX_IOPAD(0x0170, PIN_INPUT, 0) /* (Y18) RGMII2_TD1 */
+			AM62DX_IOPAD(0x0174, PIN_INPUT, 0) /* (AA18) RGMII2_TD2 */
+			AM62DX_IOPAD(0x0178, PIN_INPUT, 0) /* (W17) RGMII2_TD3 */
+			AM62DX_IOPAD(0x0168, PIN_OUTPUT, 0) /* (AB19) RGMII2_TXC */
+			AM62DX_IOPAD(0x0164, PIN_OUTPUT, 0) /* (Y19) RGMII2_TX_CTL */
+		>;
+		bootph-all;
+	};
+
+	main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
+		pinctrl-single,pins = <
+			AM62DX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */
+		>;
+	};
+
+	vddshv_sdio_pins_default: vddshv-sdio-default-pins {
+		pinctrl-single,pins = <
+			AM62DX_IOPAD(0x1F4, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO1_31 */
+		>;
+		bootph-all;
+	};
+};
+
+&mcu_pmx0 {
+	status = "okay";
+
+	pmic_irq_pins_default: pmic-irq-default-pins {
+		pinctrl-single,pins = <
+			AM62DX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */
+		>;
+	};
+};
+
+&mcu_gpio0 {
+	status = "okay";
+};
+
+&main_i2c0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c0_pins_default>;
+	clock-frequency = <400000>;
+	bootph-all;
+
+	typec_pd0: usb-power-controller@3f {
+		compatible = "ti,tps6598x";
+		reg = <0x3f>;
+
+		connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			self-powered;
+			data-role = "dual";
+			power-role = "sink";
+			port {
+				usb_con_hs: endpoint {
+					remote-endpoint = <&usb0_hs_ep>;
+				};
+			};
+		};
+	};
+
+	exp1: gpio@22 {
+		compatible = "ti,tca6424";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&main_gpio1>;
+		interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
+		bootph-all;
+
+		gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
+			"","MMC1_SD_EN",
+			"VPP_EN", "GPIO_DIX_RST",
+			"IO_EXP_OPT_EN", "DIX_INT",
+			"GPIO_eMMC_RSTn", "CPLD2_DONE",
+			"CPLD2_INTN", "CPLD1_DONE",
+			"CPLD1_INTN", "USB_TYPEA_OC_INDICATION",
+			"PCM1_INT", "PCM2_INT",
+			"GPIO_PCM1_RST", "TEST_GPIO2",
+			"GPIO_PCM2_RST", "",
+			"IO_MCAN0_STB", "IO_MCAN1_STB",
+			"PD_I2C_IRQ", "IO_EXP_TEST_LED";
+	};
+
+	exp2: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		gpio-line-names = "PCM6240_BUF_IO_EN", "",
+			"CPLD1_JTAGENB", "CPLD1_PROGRAMN",
+			"CPLD2_JTAGENB", "CPLD2_PROGRAMN",
+			"", "",
+			"", "CPLD1_TCK",
+			"CPLD1_TMS", "CPLD1_TDI",
+			"CPLD1_TDO", "CPLD2_TCK",
+			"CPLD2_TMS", "CPLD2_TDI",
+			"CPLD2_TDO", "ADDR1_IO_EXP",
+			"SoC_I2C0_SCL", "SoC_I2C0_SDA";
+	};
+};
+
+&main_i2c1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c1_pins_default>;
+	clock-frequency = <100000>;
+};
+
+&main_i2c2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c2_pins_default>;
+	clock-frequency = <400000>;
+};
+
+&sdhci1 {
+	/* SD/MMC */
+	status = "okay";
+	vmmc-supply = <&vdd_mmc1>;
+	vqmmc-supply = <&vddshv_sdio>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mmc1_pins_default>;
+	disable-wp;
+	bootph-all;
+};
+
+&main_gpio0 {
+	bootph-all;
+	status = "okay";
+};
+
+&main_gpio1 {
+	bootph-all;
+	status = "okay";
+};
+
+&main_gpio_intr {
+	status = "okay";
+};
+
+&main_uart0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart0_pins_default>;
+	bootph-all;
+};
+
+&usb0 {
+	usb-role-switch;
+
+	port {
+		usb0_hs_ep: endpoint {
+			remote-endpoint = <&usb_con_hs>;
+		};
+	};
+};
+
+&mailbox0_cluster0 {
+	status = "okay";
+
+	mbox_r5_0: mbox-r5-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+&mailbox0_cluster1 {
+	status = "okay";
+
+	mbox_c7x_0: mbox-c7x-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+&mailbox0_cluster2 {
+	status = "okay";
+
+	mbox_mcu_r5_0: mbox-mcu-r5-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+&wkup_r5fss0 {
+	status = "okay";
+};
+
+&wkup_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
+	memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
+			<&wkup_r5fss0_core0_memory_region>;
+	bootph-pre-ram;
+};
+
+&mcu_r5fss0 {
+	status = "okay";
+};
+
+&mcu_r5fss0_core0 {
+	status = "okay";
+
+	mboxes = <&mailbox0_cluster2 &mbox_mcu_r5_0>;
+	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+			<&mcu_r5fss0_core0_memory_region>;
+};
+
+&c7x_0 {
+	status = "okay";
+
+	mboxes = <&mailbox0_cluster1 &mbox_c7x_0>;
+	memory-region = <&c7x_0_dma_memory_region>,
+			<&c7x_0_memory_region>;
+};
+
+&cpsw3g {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_rgmii1_pins_default &main_rgmii2_pins_default>;
+
+	cpts@3d000 {
+		/* MAP HW3_TS_PUSH to GENF1 */
+		ti,pps = <2 1>;
+	};
+};
+
+&cpsw_port1 {
+	status = "okay";
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+	status = "okay";
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&cpsw3g_phy1>;
+};
+
+&cpsw3g_mdio {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mdio0_pins_default>;
+
+	cpsw3g_phy0: ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,min-output-impedance;
+	};
+
+	cpsw3g_phy1: ethernet-phy@3 {
+		reg = <3>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,min-output-impedance;
+	};
+};
+
+/* main_rti4 is used by C7x DSP */
+&main_rti4 {
+	status = "reserved";
+};
+
+/* main_timer2 is used by C7x DSP */
+&main_timer2 {
+	status = "reserved";
+};
+
+&vpu {
+	status = "disabled";
+};
+
+&e5010 {
+	status = "disabled";
+};
-- 
2.34.1

[PATCHv4 5/6] arm64: dts: ti: Update firmware-name for IPC

[Paresh Bhagat]

Update the firmware-name properties in the dts file to point to new IPC
firmware binaries for both the mcu-r5 and c7x core.

Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
index 8fde89ecba67..c98e4c98c956 100644
--- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
@@ -487,6 +487,7 @@ &mcu_r5fss0_core0 {
 	mboxes = <&mailbox0_cluster2 &mbox_mcu_r5_0>;
 	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 			<&mcu_r5fss0_core0_memory_region>;
+	firmware-name = "am62d-mcu-r5f0_0-fw";
 };
 
 &c7x_0 {
@@ -495,6 +496,7 @@ &c7x_0 {
 	mboxes = <&mailbox0_cluster1 &mbox_c7x_0>;
 	memory-region = <&c7x_0_dma_memory_region>,
 			<&c7x_0_memory_region>;
+	firmware-name = "am62d-c71_0-fw";
 };
 
 &cpsw3g {
-- 
2.34.1

[PATCHv4 6/6] arm64: dts: ti: Add eMMC support for AM62D

[Paresh Bhagat]

Add the necessary device tree node for eMMC controller along with the
required pinmux configuration.

Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 27 ++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
index c98e4c98c956..5ceecdd68b3f 100644
--- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
@@ -20,6 +20,7 @@ aliases {
 		serial0 = &wkup_uart0;
 		serial1 = &mcu_uart0;
 		serial2 = &main_uart0;
+		mmc0 = &sdhci0;
 		mmc1 = &sdhci1;
 		rtc0 = &wkup_rtc0;
 		ethernet0 = &cpsw_port1;
@@ -226,6 +227,22 @@ AM62DX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (M20) GPMC0_CSn3.I2C2_SDA */
 		>;
 	};
 
+	main_mmc0_pins_default: main-mmc0-default-pins {
+		pinctrl-single,pins = <
+			AM62DX_IOPAD(0x0220, PIN_INPUT_PULLUP, 0) /* (Y6) MMC0_CMD */
+			AM62DX_IOPAD(0x0218, PIN_OUTPUT, 0) /* (AB7) MMC0_CLK */
+			AM62DX_IOPAD(0x0214, PIN_INPUT_PULLUP, 0) /* (AA6) MMC0_DAT0 */
+			AM62DX_IOPAD(0x0210, PIN_INPUT_PULLUP, 0) /* (AB6) MMC0_DAT1 */
+			AM62DX_IOPAD(0x020c, PIN_INPUT_PULLUP, 0) /* (Y7) MMC0_DAT2 */
+			AM62DX_IOPAD(0x0208, PIN_INPUT_PULLUP, 0) /* (AA7) MMC0_DAT3 */
+			AM62DX_IOPAD(0x0204, PIN_INPUT_PULLUP, 0) /* (Y8) MMC0_DAT4 */
+			AM62DX_IOPAD(0x0200, PIN_INPUT_PULLUP, 0) /* (W7) MMC0_DAT5 */
+			AM62DX_IOPAD(0x01fc, PIN_INPUT_PULLUP, 0) /* (W9) MMC0_DAT6 */
+			AM62DX_IOPAD(0x01f8, PIN_INPUT_PULLUP, 0) /* (AB8) MMC0_DAT7 */
+		>;
+		bootph-all;
+	};
+
 	main_mmc1_pins_default: main-mmc1-default-pins {
 		pinctrl-single,pins = <
 			AM62DX_IOPAD(0x023c, PIN_INPUT, 0) /* (C21) MMC1_CMD */
@@ -397,6 +414,16 @@ &main_i2c2 {
 	clock-frequency = <400000>;
 };
 
+&sdhci0 {
+	/* eMMC */
+	bootph-all;
+	status = "okay";
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mmc0_pins_default>;
+	disable-wp;
+};
+
 &sdhci1 {
 	/* SD/MMC */
 	status = "okay";
-- 
2.34.1

Re: [PATCHv4 2/6] dt-bindings: arm: ti: Add bindings for AM62D2 SoC

[Krzysztof Kozlowski]

On 23/06/2025 16:12, Paresh Bhagat wrote:
> The AM62D2 SoC belongs to the K3 Multicore SoC architecture with DSP core
> targeted for applications needing high-performance Digital Signal
> Processing. It is used in applications like automotive audio systems,
> professional sound equipment, radar and radio for aerospace, sonar in
> marine devices, and ultrasound in medical imaging. It also supports
> precise signal analysis in test and measurement tools.

Drop all marketing stuff.

> 
> Some highlights of AM62D2 SoC are:

This is not a product brochure.

A nit, subject: drop second/last, redundant "bindings". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18



> 
> * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single
>   core variants are provided in the same package to allow HW compatible
>   designs.
> * One Device manager Cortex-R5F for system power and resource management,
>   and one Cortex-R5F for Functional Safety or general-purpose usage.
> * DSP with Matrix Multiplication Accelerator(MMA) (up to 2 TOPS) based on
>   single core C7x.
> * 3x Multichannel Audio Serial Ports (McASP) Up to 4/6/16 Serial Data Pins
>   which can Transmit and Receive Clocks up to 50MHz, with multi-channel I2S
>   and TDM Audio inputs and outputs.
> * Integrated Giga-bit Ethernet switch supporting up to a total of two
>   external ports with TSN capable to enable audio networking features such
>   as, Ethernet Audio Video Bridging (eAVB) and Dante.
> * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, OSPI memory
>   controller, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other
>   peripherals.
> * Dedicated Centralized Hardware Security Module with support for secure
>   boot, debug security and crypto acceleration and trusted execution
>   environment.
> * One 32 bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
> * Low power mode support: Partial IO support for CAN/GPIO/UART wakeup.
> 
> This SoC is of part K3 AM62x family, which includes the AM62A and AM62P
> variants. While the AM62A and AM62D are largely similar, the AM62D is
> specifically targeted for general-purpose DSP applications, whereas the
> AM62A focuses on edge AI workloads. A key distinction is that the AM62D
> does not include multimedia components such as the video encoder/decoder,
> MJPEG encoder, Vision Processing Accelerator (VPAC) for image signal
> processing, or the display subsystem. Additionally, the AM62D has a
> different pin configuration compared to the AM62A, which impacts
> embedded software development.
> 
> This adds dt bindings for TI's AM62D2 family of devices.
> 
> More details about the SoCs can be found in the Technical Reference Manual:
> https://www.ti.com/lit/pdf/sprujd4
> 
> Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>


And what happened with the previous comments?

Reach internally TI so they will coach you how to send patches upstream.

Best regards,
Krzysztof

Re: [PATCHv4 6/6] arm64: dts: ti: Add eMMC support for AM62D

[Bryan Brattlof]

On June 23, 2025 thus sayeth Paresh Bhagat:
> Add the necessary device tree node for eMMC controller along with the
> required pinmux configuration.
> 

Could this be squashed in 4/6?

> Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 27 ++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
> index c98e4c98c956..5ceecdd68b3f 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
> @@ -20,6 +20,7 @@ aliases {
>  		serial0 = &wkup_uart0;
>  		serial1 = &mcu_uart0;
>  		serial2 = &main_uart0;
> +		mmc0 = &sdhci0;
>  		mmc1 = &sdhci1;
>  		rtc0 = &wkup_rtc0;
>  		ethernet0 = &cpsw_port1;
> @@ -226,6 +227,22 @@ AM62DX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (M20) GPMC0_CSn3.I2C2_SDA */
>  		>;
>  	};
>  
> +	main_mmc0_pins_default: main-mmc0-default-pins {
> +		pinctrl-single,pins = <
> +			AM62DX_IOPAD(0x0220, PIN_INPUT_PULLUP, 0) /* (Y6) MMC0_CMD */
> +			AM62DX_IOPAD(0x0218, PIN_OUTPUT, 0) /* (AB7) MMC0_CLK */
> +			AM62DX_IOPAD(0x0214, PIN_INPUT_PULLUP, 0) /* (AA6) MMC0_DAT0 */
> +			AM62DX_IOPAD(0x0210, PIN_INPUT_PULLUP, 0) /* (AB6) MMC0_DAT1 */
> +			AM62DX_IOPAD(0x020c, PIN_INPUT_PULLUP, 0) /* (Y7) MMC0_DAT2 */
> +			AM62DX_IOPAD(0x0208, PIN_INPUT_PULLUP, 0) /* (AA7) MMC0_DAT3 */
> +			AM62DX_IOPAD(0x0204, PIN_INPUT_PULLUP, 0) /* (Y8) MMC0_DAT4 */
> +			AM62DX_IOPAD(0x0200, PIN_INPUT_PULLUP, 0) /* (W7) MMC0_DAT5 */
> +			AM62DX_IOPAD(0x01fc, PIN_INPUT_PULLUP, 0) /* (W9) MMC0_DAT6 */
> +			AM62DX_IOPAD(0x01f8, PIN_INPUT_PULLUP, 0) /* (AB8) MMC0_DAT7 */
> +		>;
> +		bootph-all;
> +	};
> +
>  	main_mmc1_pins_default: main-mmc1-default-pins {
>  		pinctrl-single,pins = <
>  			AM62DX_IOPAD(0x023c, PIN_INPUT, 0) /* (C21) MMC1_CMD */
> @@ -397,6 +414,16 @@ &main_i2c2 {
>  	clock-frequency = <400000>;
>  };
>  
> +&sdhci0 {
> +	/* eMMC */
> +	bootph-all;
> +	status = "okay";
> +	non-removable;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&main_mmc0_pins_default>;
> +	disable-wp;
> +};

Make sure we follow the ordering of these properties:

    https://www.kernel.org/doc/html/latest/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node

> +
>  &sdhci1 {
>  	/* SD/MMC */
>  	status = "okay";
> -- 
> 2.34.1
> 

Re: [PATCHv4 5/6] arm64: dts: ti: Update firmware-name for IPC

[Bryan Brattlof]

On June 23, 2025 thus sayeth Paresh Bhagat:
> Update the firmware-name properties in the dts file to point to new IPC
> firmware binaries for both the mcu-r5 and c7x core.
> 

Same here. This seems like we should have squashed this into 4/6

~Bryan

> Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
> index 8fde89ecba67..c98e4c98c956 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
> @@ -487,6 +487,7 @@ &mcu_r5fss0_core0 {
>  	mboxes = <&mailbox0_cluster2 &mbox_mcu_r5_0>;
>  	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
>  			<&mcu_r5fss0_core0_memory_region>;
> +	firmware-name = "am62d-mcu-r5f0_0-fw";
>  };
>  
>  &c7x_0 {
> @@ -495,6 +496,7 @@ &c7x_0 {
>  	mboxes = <&mailbox0_cluster1 &mbox_c7x_0>;
>  	memory-region = <&c7x_0_dma_memory_region>,
>  			<&c7x_0_memory_region>;
> +	firmware-name = "am62d-c71_0-fw";
>  };
>  
>  &cpsw3g {
> -- 
> 2.34.1
> 

Re: [PATCHv4 1/6] arm64: dts: ti: Add bootph property to nodes at source for am62a

[Bryan Brattlof]

On June 23, 2025 thus sayeth Paresh Bhagat:
> Add bootph property directly into the original definitions of relevant
> nodes (e.g., power domains, USB controllers, and other peripherals)
> within their respective DTSI files (ex. main, mcu, and wakeup)i for
> am62a.
> 
> By defining bootph in the nodes source definitions instead of appending
> it later in final DTS files, this change ensures that the property is
> inherently present wherever the nodes are reused across derived device
> trees.
> 
> Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-am62a-main.dtsi   | 15 +++++++++++++++
>  arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi    |  1 +
>  arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi |  3 +++
>  arch/arm64/boot/dts/ti/k3-am62a.dtsi        |  3 +++
>  4 files changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
> index 63e097ddf988..1b7fe4487475 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
> @@ -51,6 +51,7 @@ phy_gmii_sel: phy@4044 {
>  			compatible = "ti,am654-phy-gmii-sel";
>  			reg = <0x4044 0x8>;
>  			#phy-cells = <1>;
> +			bootph-all;
>  		};
>  
>  		epwm_tbclk: clock-controller@4130 {
> @@ -84,6 +85,7 @@ dmss: bus@48000000 {
>  		#size-cells = <2>;
>  		dma-ranges;
>  		ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>;
> +		bootph-all;
>  
>  		ti,sci-dev-id = <25>;
>  
> @@ -96,6 +98,7 @@ secure_proxy_main: mailbox@4d000000 {
>  			#mbox-cells = <1>;
>  			interrupt-names = "rx_012";
>  			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +			bootph-all;
>  		};
>  
>  		inta_main_dmss: interrupt-controller@48000000 {
> @@ -131,6 +134,7 @@ main_bcdma: dma-controller@485c0100 {
>  			ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
>  			ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
>  			ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
> +			bootph-all;
>  		};
>  
>  		main_pktdma: dma-controller@485c0000 {
> @@ -167,6 +171,7 @@ main_pktdma: dma-controller@485c0000 {
>  						<0x2c>, /* FLOW_CPSW_RX_CHAN */
>  						<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
>  						<0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
> +			bootph-all;
>  		};
>  	};
>  
> @@ -216,20 +221,24 @@ dmsc: system-controller@44043000 {
>  		mbox-names = "rx", "tx";
>  		mboxes = <&secure_proxy_main 12>,
>  			 <&secure_proxy_main 13>;
> +		bootph-all;
>  
>  		k3_pds: power-controller {
>  			compatible = "ti,sci-pm-domain";
>  			#power-domain-cells = <2>;
> +			bootph-all;
>  		};
>  
>  		k3_clks: clock-controller {
>  			compatible = "ti,k2g-sci-clk";
>  			#clock-cells = <2>;
> +			bootph-all;
>  		};
>  
>  		k3_reset: reset-controller {
>  			compatible = "ti,sci-reset";
>  			#reset-cells = <2>;
> +			bootph-all;
>  		};
>  	};
>  
> @@ -254,6 +263,7 @@ secure_proxy_sa3: mailbox@43600000 {
>  		 * firmware on non-MPU processors
>  		 */
>  		status = "disabled";
> +		bootph-all;
>  	};
>  
>  	main_pmx0: pinctrl@f4000 {
> @@ -262,6 +272,7 @@ main_pmx0: pinctrl@f4000 {
>  		#pinctrl-cells = <1>;
>  		pinctrl-single,register-width = <32>;
>  		pinctrl-single,function-mask = <0xffffffff>;
> +		bootph-all;
>  	};
>  
>  	main_esm: esm@420000 {
> @@ -282,6 +293,7 @@ main_timer0: timer@2400000 {
>  		assigned-clock-parents = <&k3_clks 36 3>;
>  		power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
>  		ti,timer-pwm;
> +		bootph-all;
>  	};
>  
>  	main_timer1: timer@2410000 {
> @@ -653,6 +665,7 @@ usb0: usb@31000000 {
>  			dr_mode = "otg";
>  			snps,usb2-gadget-lpm-disable;
>  			snps,usb2-lpm-disable;
> +			bootph-all;
>  		};
>  	};
>  
> @@ -745,6 +758,7 @@ cpsw_port1: port@1 {
>  				phys = <&phy_gmii_sel 1>;
>  				mac-address = [00 00 00 00 00 00];
>  				ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
> +				bootph-all;
>  			};
>  
>  			cpsw_port2: port@2 {
> @@ -764,6 +778,7 @@ cpsw3g_mdio: mdio@f00 {
>  			clocks = <&k3_clks 13 0>;
>  			clock-names = "fck";
>  			bus_freq = <1000000>;
> +			bootph-all;
>  		};
>  
>  		cpts@3d000 {
> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi
> index ee961ced7208..df4aa131097f 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi
> @@ -12,6 +12,7 @@ mcu_pmx0: pinctrl@4084000 {
>  		#pinctrl-cells = <1>;
>  		pinctrl-single,register-width = <32>;
>  		pinctrl-single,function-mask = <0xffffffff>;
> +		bootph-all;
>  	};
>  
>  	mcu_esm: esm@4100000 {
> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
> index 259ae6ebbfb5..86aae252385c 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
> @@ -13,10 +13,12 @@ wkup_conf: bus@43000000 {
>  		#address-cells = <1>;
>  		#size-cells = <1>;
>  		ranges = <0x00 0x00 0x43000000 0x20000>;
> +		bootph-all;
>  
>  		chipid: chipid@14 {
>  			compatible = "ti,am654-chipid";
>  			reg = <0x14 0x4>;
> +			bootph-all;
>  		};
>  
>  		opp_efuse_table: syscon@18 {
> @@ -67,6 +69,7 @@ wkup_uart0: serial@0 {
>  			reg = <0 0x100>;
>  			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
>  			status = "disabled";
> +			bootph-pre-ram;
>  	       };
>  	};
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am62a.dtsi b/arch/arm64/boot/dts/ti/k3-am62a.dtsi
> index 4d79b3e9486a..54eab2c93eff 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62a.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62a.dtsi
> @@ -50,6 +50,7 @@ cbass_main: bus@f0000 {
>  		compatible = "simple-bus";
>  		#address-cells = <2>;
>  		#size-cells = <2>;
> +		bootph-all;

We only need to add the bootph-* properties to the leaf nodes. U-Boot is 
smart enough to propagate these properties all the way to the root when 
it's pruning the device tree for the bootloaders.

~Bryan

Re: [PATCHv4 4/6] arm64: dts: ti: Add support for AM62D2-EVM

[Andrew Lunn]

> +&cpsw_port1 {
> +	status = "okay";
> +	phy-mode = "rgmii-rxid";
> +	phy-handle = <&cpsw3g_phy0>;

Does the PCB have extra long RX clock lines?

More likely, this should be 'rgmii-id', and you should delete the
ti,rx-internal-delay in the PHY node, allowing it to insert the 2ns
delay in the normal way.

	Andrew

Re: [PATCHv4 6/6] arm64: dts: ti: Add eMMC support for AM62D

[Paresh Bhagat]

Hi Bryan,


On 23/06/25 19:58, Bryan Brattlof wrote:
> On June 23, 2025 thus sayeth Paresh Bhagat:
>> Add the necessary device tree node for eMMC controller along with the
>> required pinmux configuration.
>>
> Could this be squashed in 4/6?


Yep will do


>
>> Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 27 ++++++++++++++++++++++++
>>   1 file changed, 27 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
>> index c98e4c98c956..5ceecdd68b3f 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
>> @@ -20,6 +20,7 @@ aliases {
>>   		serial0 = &wkup_uart0;
>>   		serial1 = &mcu_uart0;
>>   		serial2 = &main_uart0;
>> +		mmc0 = &sdhci0;
>>   		mmc1 = &sdhci1;
>>   		rtc0 = &wkup_rtc0;
>>   		ethernet0 = &cpsw_port1;
>> @@ -226,6 +227,22 @@ AM62DX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (M20) GPMC0_CSn3.I2C2_SDA */
>>   		>;
>>   	};
>>   
>> +	main_mmc0_pins_default: main-mmc0-default-pins {
>> +		pinctrl-single,pins = <
>> +			AM62DX_IOPAD(0x0220, PIN_INPUT_PULLUP, 0) /* (Y6) MMC0_CMD */
>> +			AM62DX_IOPAD(0x0218, PIN_OUTPUT, 0) /* (AB7) MMC0_CLK */
>> +			AM62DX_IOPAD(0x0214, PIN_INPUT_PULLUP, 0) /* (AA6) MMC0_DAT0 */
>> +			AM62DX_IOPAD(0x0210, PIN_INPUT_PULLUP, 0) /* (AB6) MMC0_DAT1 */
>> +			AM62DX_IOPAD(0x020c, PIN_INPUT_PULLUP, 0) /* (Y7) MMC0_DAT2 */
>> +			AM62DX_IOPAD(0x0208, PIN_INPUT_PULLUP, 0) /* (AA7) MMC0_DAT3 */
>> +			AM62DX_IOPAD(0x0204, PIN_INPUT_PULLUP, 0) /* (Y8) MMC0_DAT4 */
>> +			AM62DX_IOPAD(0x0200, PIN_INPUT_PULLUP, 0) /* (W7) MMC0_DAT5 */
>> +			AM62DX_IOPAD(0x01fc, PIN_INPUT_PULLUP, 0) /* (W9) MMC0_DAT6 */
>> +			AM62DX_IOPAD(0x01f8, PIN_INPUT_PULLUP, 0) /* (AB8) MMC0_DAT7 */
>> +		>;
>> +		bootph-all;
>> +	};
>> +
>>   	main_mmc1_pins_default: main-mmc1-default-pins {
>>   		pinctrl-single,pins = <
>>   			AM62DX_IOPAD(0x023c, PIN_INPUT, 0) /* (C21) MMC1_CMD */
>> @@ -397,6 +414,16 @@ &main_i2c2 {
>>   	clock-frequency = <400000>;
>>   };
>>   
>> +&sdhci0 {
>> +	/* eMMC */
>> +	bootph-all;
>> +	status = "okay";
>> +	non-removable;
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&main_mmc0_pins_default>;
>> +	disable-wp;
>> +};
> Make sure we follow the ordering of these properties:
>
>      https://www.kernel.org/doc/html/latest/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node


Will fix this. Thanks


>
>> +
>>   &sdhci1 {
>>   	/* SD/MMC */
>>   	status = "okay";
>> -- 
>> 2.34.1
>>

Re: [PATCHv4 5/6] arm64: dts: ti: Update firmware-name for IPC

[Paresh Bhagat]

Hi Bryan,


On 23/06/25 19:59, Bryan Brattlof wrote:
> On June 23, 2025 thus sayeth Paresh Bhagat:
>> Update the firmware-name properties in the dts file to point to new IPC
>> firmware binaries for both the mcu-r5 and c7x core.
>>
> Same here. This seems like we should have squashed this into 4/6
>
> ~Bryan
Yep will do
>
>> Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
>> index 8fde89ecba67..c98e4c98c956 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
>> @@ -487,6 +487,7 @@ &mcu_r5fss0_core0 {
>>   	mboxes = <&mailbox0_cluster2 &mbox_mcu_r5_0>;
>>   	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
>>   			<&mcu_r5fss0_core0_memory_region>;
>> +	firmware-name = "am62d-mcu-r5f0_0-fw";
>>   };
>>   
>>   &c7x_0 {
>> @@ -495,6 +496,7 @@ &c7x_0 {
>>   	mboxes = <&mailbox0_cluster1 &mbox_c7x_0>;
>>   	memory-region = <&c7x_0_dma_memory_region>,
>>   			<&c7x_0_memory_region>;
>> +	firmware-name = "am62d-c71_0-fw";
>>   };
>>   
>>   &cpsw3g {
>> -- 
>> 2.34.1
>>

Re: [PATCHv4 1/6] arm64: dts: ti: Add bootph property to nodes at source for am62a

[Paresh Bhagat]

Hi Bryan,


On 23/06/25 20:15, Bryan Brattlof wrote:
> On June 23, 2025 thus sayeth Paresh Bhagat:
>> Add bootph property directly into the original definitions of relevant
>> nodes (e.g., power domains, USB controllers, and other peripherals)
>> within their respective DTSI files (ex. main, mcu, and wakeup)i for
>> am62a.
>>
>> By defining bootph in the nodes source definitions instead of appending
>> it later in final DTS files, this change ensures that the property is
>> inherently present wherever the nodes are reused across derived device
>> trees.
>>
>> Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-am62a-main.dtsi   | 15 +++++++++++++++
>>   arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi    |  1 +
>>   arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi |  3 +++
>>   arch/arm64/boot/dts/ti/k3-am62a.dtsi        |  3 +++
>>   4 files changed, 22 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>> index 63e097ddf988..1b7fe4487475 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>> @@ -51,6 +51,7 @@ phy_gmii_sel: phy@4044 {
>>   			compatible = "ti,am654-phy-gmii-sel";
>>   			reg = <0x4044 0x8>;
>>   			#phy-cells = <1>;
>> +			bootph-all;
>>   		};
>>   
>>   		epwm_tbclk: clock-controller@4130 {
>> @@ -84,6 +85,7 @@ dmss: bus@48000000 {
>>   		#size-cells = <2>;
>>   		dma-ranges;
>>   		ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>;
>> +		bootph-all;
>>   
>>   		ti,sci-dev-id = <25>;
>>   
>> @@ -96,6 +98,7 @@ secure_proxy_main: mailbox@4d000000 {
>>   			#mbox-cells = <1>;
>>   			interrupt-names = "rx_012";
>>   			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
>> +			bootph-all;
>>   		};
>>   
>>   		inta_main_dmss: interrupt-controller@48000000 {
>> @@ -131,6 +134,7 @@ main_bcdma: dma-controller@485c0100 {
>>   			ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
>>   			ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
>>   			ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
>> +			bootph-all;
>>   		};
>>   
>>   		main_pktdma: dma-controller@485c0000 {
>> @@ -167,6 +171,7 @@ main_pktdma: dma-controller@485c0000 {
>>   						<0x2c>, /* FLOW_CPSW_RX_CHAN */
>>   						<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
>>   						<0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
>> +			bootph-all;
>>   		};
>>   	};
>>   
>> @@ -216,20 +221,24 @@ dmsc: system-controller@44043000 {
>>   		mbox-names = "rx", "tx";
>>   		mboxes = <&secure_proxy_main 12>,
>>   			 <&secure_proxy_main 13>;
>> +		bootph-all;
>>   
>>   		k3_pds: power-controller {
>>   			compatible = "ti,sci-pm-domain";
>>   			#power-domain-cells = <2>;
>> +			bootph-all;
>>   		};
>>   
>>   		k3_clks: clock-controller {
>>   			compatible = "ti,k2g-sci-clk";
>>   			#clock-cells = <2>;
>> +			bootph-all;
>>   		};
>>   
>>   		k3_reset: reset-controller {
>>   			compatible = "ti,sci-reset";
>>   			#reset-cells = <2>;
>> +			bootph-all;
>>   		};
>>   	};
>>   
>> @@ -254,6 +263,7 @@ secure_proxy_sa3: mailbox@43600000 {
>>   		 * firmware on non-MPU processors
>>   		 */
>>   		status = "disabled";
>> +		bootph-all;
>>   	};
>>   
>>   	main_pmx0: pinctrl@f4000 {
>> @@ -262,6 +272,7 @@ main_pmx0: pinctrl@f4000 {
>>   		#pinctrl-cells = <1>;
>>   		pinctrl-single,register-width = <32>;
>>   		pinctrl-single,function-mask = <0xffffffff>;
>> +		bootph-all;
>>   	};
>>   
>>   	main_esm: esm@420000 {
>> @@ -282,6 +293,7 @@ main_timer0: timer@2400000 {
>>   		assigned-clock-parents = <&k3_clks 36 3>;
>>   		power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
>>   		ti,timer-pwm;
>> +		bootph-all;
>>   	};
>>   
>>   	main_timer1: timer@2410000 {
>> @@ -653,6 +665,7 @@ usb0: usb@31000000 {
>>   			dr_mode = "otg";
>>   			snps,usb2-gadget-lpm-disable;
>>   			snps,usb2-lpm-disable;
>> +			bootph-all;
>>   		};
>>   	};
>>   
>> @@ -745,6 +758,7 @@ cpsw_port1: port@1 {
>>   				phys = <&phy_gmii_sel 1>;
>>   				mac-address = [00 00 00 00 00 00];
>>   				ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
>> +				bootph-all;
>>   			};
>>   
>>   			cpsw_port2: port@2 {
>> @@ -764,6 +778,7 @@ cpsw3g_mdio: mdio@f00 {
>>   			clocks = <&k3_clks 13 0>;
>>   			clock-names = "fck";
>>   			bus_freq = <1000000>;
>> +			bootph-all;
>>   		};
>>   
>>   		cpts@3d000 {
>> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi
>> index ee961ced7208..df4aa131097f 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi
>> @@ -12,6 +12,7 @@ mcu_pmx0: pinctrl@4084000 {
>>   		#pinctrl-cells = <1>;
>>   		pinctrl-single,register-width = <32>;
>>   		pinctrl-single,function-mask = <0xffffffff>;
>> +		bootph-all;
>>   	};
>>   
>>   	mcu_esm: esm@4100000 {
>> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
>> index 259ae6ebbfb5..86aae252385c 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
>> @@ -13,10 +13,12 @@ wkup_conf: bus@43000000 {
>>   		#address-cells = <1>;
>>   		#size-cells = <1>;
>>   		ranges = <0x00 0x00 0x43000000 0x20000>;
>> +		bootph-all;
>>   
>>   		chipid: chipid@14 {
>>   			compatible = "ti,am654-chipid";
>>   			reg = <0x14 0x4>;
>> +			bootph-all;
>>   		};
>>   
>>   		opp_efuse_table: syscon@18 {
>> @@ -67,6 +69,7 @@ wkup_uart0: serial@0 {
>>   			reg = <0 0x100>;
>>   			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
>>   			status = "disabled";
>> +			bootph-pre-ram;
>>   	       };
>>   	};
>>   
>> diff --git a/arch/arm64/boot/dts/ti/k3-am62a.dtsi b/arch/arm64/boot/dts/ti/k3-am62a.dtsi
>> index 4d79b3e9486a..54eab2c93eff 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am62a.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am62a.dtsi
>> @@ -50,6 +50,7 @@ cbass_main: bus@f0000 {
>>   		compatible = "simple-bus";
>>   		#address-cells = <2>;
>>   		#size-cells = <2>;
>> +		bootph-all;
> We only need to add the bootph-* properties to the leaf nodes. U-Boot is
> smart enough to propagate these properties all the way to the root when
> it's pruning the device tree for the bootloaders.
>
> ~Bryan


Will fix this. Thanks

Re: [PATCHv4 2/6] dt-bindings: arm: ti: Add bindings for AM62D2 SoC

[Paresh Bhagat]

Hi Krzysztof,

Thanks for the review.

On 23/06/25 19:55, Krzysztof Kozlowski wrote:
> On 23/06/2025 16:12, Paresh Bhagat wrote:
>> The AM62D2 SoC belongs to the K3 Multicore SoC architecture with DSP core
>> targeted for applications needing high-performance Digital Signal
>> Processing. It is used in applications like automotive audio systems,
>> professional sound equipment, radar and radio for aerospace, sonar in
>> marine devices, and ultrasound in medical imaging. It also supports
>> precise signal analysis in test and measurement tools.
> Drop all marketing stuff.
>
>> Some highlights of AM62D2 SoC are:
> This is not a product brochure.
>
> A nit, subject: drop second/last, redundant "bindings". The
> "dt-bindings" prefix is already stating that these are bindings.
> See also:
> https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18


Will fix this in next version. Thanks
>
>
>
>> * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single
>>    core variants are provided in the same package to allow HW compatible
>>    designs.
>> * One Device manager Cortex-R5F for system power and resource management,
>>    and one Cortex-R5F for Functional Safety or general-purpose usage.
>> * DSP with Matrix Multiplication Accelerator(MMA) (up to 2 TOPS) based on
>>    single core C7x.
>> * 3x Multichannel Audio Serial Ports (McASP) Up to 4/6/16 Serial Data Pins
>>    which can Transmit and Receive Clocks up to 50MHz, with multi-channel I2S
>>    and TDM Audio inputs and outputs.
>> * Integrated Giga-bit Ethernet switch supporting up to a total of two
>>    external ports with TSN capable to enable audio networking features such
>>    as, Ethernet Audio Video Bridging (eAVB) and Dante.
>> * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, OSPI memory
>>    controller, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other
>>    peripherals.
>> * Dedicated Centralized Hardware Security Module with support for secure
>>    boot, debug security and crypto acceleration and trusted execution
>>    environment.
>> * One 32 bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
>> * Low power mode support: Partial IO support for CAN/GPIO/UART wakeup.

I will refine the first two paragraphs to be very concise.


>>
>> This SoC is of part K3 AM62x family, which includes the AM62A and AM62P
>> variants. While the AM62A and AM62D are largely similar, the AM62D is
>> specifically targeted for general-purpose DSP applications, whereas the
>> AM62A focuses on edge AI workloads. A key distinction is that the AM62D
>> does not include multimedia components such as the video encoder/decoder,
>> MJPEG encoder, Vision Processing Accelerator (VPAC) for image signal
>> processing, or the display subsystem. Additionally, the AM62D has a
>> different pin configuration compared to the AM62A, which impacts
>> embedded software development.


This section is important as it clarifies the difference between AM62a 
and AM62d, as we are reusing AM62a dtsi files for AM62d. Let me know if 
you need a shorter version.


>>
>> This adds dt bindings for TI's AM62D2 family of devices.
>>
>> More details about the SoCs can be found in the Technical Reference Manual:
>> https://www.ti.com/lit/pdf/sprujd4
>>
>> Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
>
> And what happened with the previous comments?


Yep there were some indentation problems earlier, which is fixed in this 
version. There was also an ack from Conor Dooley in v3. I will include that.


>
> Reach internally TI so they will coach you how to send patches upstream.
>
> Best regards,
> Krzysztof

Re: [PATCHv4 2/6] dt-bindings: arm: ti: Add bindings for AM62D2 SoC

[Krzysztof Kozlowski]

On 24/06/2025 12:39, Paresh Bhagat wrote:
> 
>>>
>>> This SoC is of part K3 AM62x family, which includes the AM62A and AM62P
>>> variants. While the AM62A and AM62D are largely similar, the AM62D is
>>> specifically targeted for general-purpose DSP applications, whereas the
>>> AM62A focuses on edge AI workloads. A key distinction is that the AM62D
>>> does not include multimedia components such as the video encoder/decoder,
>>> MJPEG encoder, Vision Processing Accelerator (VPAC) for image signal
>>> processing, or the display subsystem. Additionally, the AM62D has a
>>> different pin configuration compared to the AM62A, which impacts
>>> embedded software development.
> 
> 
> This section is important as it clarifies the difference between AM62a 
> and AM62d, as we are reusing AM62a dtsi files for AM62d. Let me know if 
> you need a shorter version.

This is not important:

"While the AM62A and AM62D are largely similar, the AM62D is
specifically targeted for general-purpose DSP applications, whereas the
AM62A focuses on edge AI workloads."

It is irrelevant. Rest is fine.

> 
> 
>>>
>>> This adds dt bindings for TI's AM62D2 family of devices.
>>>
>>> More details about the SoCs can be found in the Technical Reference Manual:
>>> https://www.ti.com/lit/pdf/sprujd4
>>>
>>> Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
>>
>> And what happened with the previous comments?
> 
> 
> Yep there were some indentation problems earlier, which is fixed in this 
> version. There was also an ack from Conor Dooley in v3. I will include that.

Why you did not include it before?

Can you start using b4 for your process of submitting patches?


Best regards,
Krzysztof

Re: [PATCHv4 2/6] dt-bindings: arm: ti: Add bindings for AM62D2 SoC

[Paresh Bhagat]

Hi Krzysztof,


On 24/06/25 16:25, Krzysztof Kozlowski wrote:
> On 24/06/2025 12:39, Paresh Bhagat wrote:
>>>> This SoC is of part K3 AM62x family, which includes the AM62A and AM62P
>>>> variants. While the AM62A and AM62D are largely similar, the AM62D is
>>>> specifically targeted for general-purpose DSP applications, whereas the
>>>> AM62A focuses on edge AI workloads. A key distinction is that the AM62D
>>>> does not include multimedia components such as the video encoder/decoder,
>>>> MJPEG encoder, Vision Processing Accelerator (VPAC) for image signal
>>>> processing, or the display subsystem. Additionally, the AM62D has a
>>>> different pin configuration compared to the AM62A, which impacts
>>>> embedded software development.
>>
>> This section is important as it clarifies the difference between AM62a
>> and AM62d, as we are reusing AM62a dtsi files for AM62d. Let me know if
>> you need a shorter version.
> This is not important:
>
> "While the AM62A and AM62D are largely similar, the AM62D is
> specifically targeted for general-purpose DSP applications, whereas the
> AM62A focuses on edge AI workloads."
>
> It is irrelevant. Rest is fine.
Fine will do.
>
>>
>>>> This adds dt bindings for TI's AM62D2 family of devices.
>>>>
>>>> More details about the SoCs can be found in the Technical Reference Manual:
>>>> https://www.ti.com/lit/pdf/sprujd4
>>>>
>>>> Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
>>> And what happened with the previous comments?
>>
>> Yep there were some indentation problems earlier, which is fixed in this
>> version. There was also an ack from Conor Dooley in v3. I will include that.
> Why you did not include it before?
>
> Can you start using b4 for your process of submitting patches?


I missed it. I got to know about the b4 tool internally, will use it. 
Thanks.
>
>
> Best regards,
> Krzysztof

Re: [EXTERNAL] Re: [PATCHv4 4/6] arm64: dts: ti: Add support for AM62D2-EVM

[Paresh Bhagat]

Hi Andrew,

On 24/06/25 13:51, Andrew Lunn wrote:
> > +&cpsw_port1 { > + status = "okay"; > + phy-mode = "rgmii-rxid"; > + 
> phy-handle = <&cpsw3g_phy0>; Does the PCB have extra long RX clock 
> lines? More likely, this should be 'rgmii-id', and you should delete 
> the ti,rx-internal-delay
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> > +&cpsw_port1 {
> > +	status = "okay";
> > +	phy-mode = "rgmii-rxid";
> > +	phy-handle = <&cpsw3g_phy0>;
>
> Does the PCB have extra long RX clock lines?
>
> More likely, this should be 'rgmii-id', and you should delete the
> ti,rx-internal-delay in the PHY node, allowing it to insert the 2ns
> delay in the normal way.
>
> 	Andrew

I assume you are referring to the changes in a patch here
https://lore.kernel.org/r/cover.1750756583.git.matthias.schiffer@ew.tq-group.com/

Will fix this in next version. Thanks for the review.