From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 130CEC7EE32 for ; Thu, 26 Jun 2025 12:27:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Qu2L3R5zU3pfooW941saPxIblz4kIELfHaA2n8pmdWY=; b=WxkVRXIz+yZHyXW0KvbKIyrORi 9yMsEftoMRY8cxizxApDGUl4SpIJ3g1plJQj975teN2duCJvE027TyPaRCk1M67Wbexk3si86docx SkCUsALbmm5K7bx6/2CTvPtDZHTeNO3QHtfcQOwixBZOpVX2I6CF+1NrLbduH+3pRcUIkTkIEkIhA iqoLDfYwRXjEZgIp7c8bvL77NPg3tsdYzBt/+7KYCf/sgNx47VRaNpSL1gAFlXcfDPemaZNn+k4xA ruEjQCOnfPYDu9AoRxdVWIupMMB8VJB8eIprwiMGAgISycDxfDJUkMOJc/5ds/WMI7YzRHGrGbtv8 jiH85ZWQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uUlhI-0000000BXPE-0Lzq; Thu, 26 Jun 2025 12:27:20 +0000 Received: from sea.source.kernel.org ([2600:3c0a:e001:78e:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uUjpk-0000000BHGf-3QqB for linux-arm-kernel@lists.infradead.org; Thu, 26 Jun 2025 10:27:57 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 85E424441A; Thu, 26 Jun 2025 10:27:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B09BBC4CEEB; Thu, 26 Jun 2025 10:27:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750933676; bh=/dE8LD/ePWA/0RVJBLeEqlL5qzeRTK7k8l1BILw0Xkg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=NBx8KwQ/BAWKpevPsWEBVC9utzRnBHepvygNP57P/2sLF53lXXu3qu1MVTFcbEhNh Yb8cE/j5BPrM9lLmyNmgJDuI8t8Wxnk3VqZK+57ecgCoeHW1AT9pS2u4Se/V5FtvyB diDPuMIBSGRsZja2dXCYTEiq37g2YChq+sl/qwn8tWJydbjOUdLwyFOiazAmy0B4yY npE2GgpwQqeTyIhkE+45IRDz2EU9mqg9Spl42Mx1rbcX80OckjZq35jC9JUAFZvlu2 dcSDf3Ypge5sPoB8HFHvN9Jice1VGqOgZyBIDA7YTIRnAQ24O3lNFSWqDbVoCUyJjh tljtPloGkyP7A== From: Lorenzo Pieralisi Date: Thu, 26 Jun 2025 12:26:08 +0200 Subject: [PATCH v6 17/31] arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250626-gicv5-host-v6-17-48e046af4642@kernel.org> References: <20250626-gicv5-host-v6-0-48e046af4642@kernel.org> In-Reply-To: <20250626-gicv5-host-v6-0-48e046af4642@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Jonathan Cameron , Timothy Hayes , Bjorn Helgaas , "Liam R. Howlett" , Peter Maydell , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.15-dev-6f78e X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250626_032756_880733_569A7EFC X-CRM114-Status: GOOD ( 10.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Implement the GCIE capability as a strict boot cpu capability to detect whether architectural GICv5 support is available in HW. Plug it in with a naming consistent with the existing GICv3 CPU interface capability. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/kernel/cpufeature.c | 7 +++++++ arch/arm64/tools/cpucaps | 1 + 2 files changed, 8 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 42ba76b6c8cd..2fa26129762c 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -3061,6 +3061,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_pmuv3, }, #endif + { + .desc = "GICv5 CPU interface", + .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, + .capability = ARM64_HAS_GICV5_CPUIF, + .matches = has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) + }, {}, }; diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index a7a4d9e6e12e..8665e4cfbeab 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -36,6 +36,7 @@ HAS_GENERIC_AUTH_ARCH_QARMA3 HAS_GENERIC_AUTH_ARCH_QARMA5 HAS_GENERIC_AUTH_IMP_DEF HAS_GICV3_CPUIF +HAS_GICV5_CPUIF HAS_GIC_PRIO_MASKING HAS_GIC_PRIO_RELAXED_SYNC HAS_HCR_NV1 -- 2.48.0