* [PATCH 1/1] dt-bindings: mtd: convert lpc32xx-mlc.txt to yaml format
@ 2025-06-23 20:26 Frank Li
2025-06-27 2:52 ` Rob Herring
0 siblings, 1 reply; 2+ messages in thread
From: Frank Li @ 2025-06-23 20:26 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vladimir Zapolskiy, Piotr Wojtaszczyk,
open list:MEMORY TECHNOLOGY DEVICES (MTD),
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/LPC32XX SOC SUPPORT, open list
Cc: imx
Convert lpc32xx-mlc.txt to yaml format.
Additional changes:
- add ref to nand-controller.yaml.
- replace _ with - in property names.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
.../devicetree/bindings/mtd/lpc32xx-mlc.txt | 50 ------------
.../bindings/mtd/nxp,lpc3220-mlc.yaml | 81 +++++++++++++++++++
2 files changed, 81 insertions(+), 50 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt
create mode 100644 Documentation/devicetree/bindings/mtd/nxp,lpc3220-mlc.yaml
diff --git a/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt b/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt
deleted file mode 100644
index 64c06aa05ac71..0000000000000
--- a/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-NXP LPC32xx SoC NAND MLC controller
-
-Required properties:
-- compatible: "nxp,lpc3220-mlc"
-- reg: Address and size of the controller
-- interrupts: The NAND interrupt specification
-- gpios: GPIO specification for NAND write protect
-
-The following required properties are very controller specific. See the LPC32xx
-User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
-Hz, to make them independent of actual clock speed and to provide for good
-accuracy:)
-- nxp,tcea_delay: TCEA_DELAY
-- nxp,busy_delay: BUSY_DELAY
-- nxp,nand_ta: NAND_TA
-- nxp,rd_high: RD_HIGH
-- nxp,rd_low: RD_LOW
-- nxp,wr_high: WR_HIGH
-- nxp,wr_low: WR_LOW
-
-Optional subnodes:
-- Partitions, see Documentation/devicetree/bindings/mtd/mtd.yaml
-
-Example:
-
- mlc: flash@200a8000 {
- compatible = "nxp,lpc3220-mlc";
- reg = <0x200A8000 0x11000>;
- interrupts = <11 0>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- nxp,tcea-delay = <333333333>;
- nxp,busy-delay = <10000000>;
- nxp,nand-ta = <18181818>;
- nxp,rd-high = <31250000>;
- nxp,rd-low = <45454545>;
- nxp,wr-high = <40000000>;
- nxp,wr-low = <83333333>;
- gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
-
- mtd0@00000000 {
- label = "boot";
- reg = <0x00000000 0x00064000>;
- read-only;
- };
-
- ...
-
- };
diff --git a/Documentation/devicetree/bindings/mtd/nxp,lpc3220-mlc.yaml b/Documentation/devicetree/bindings/mtd/nxp,lpc3220-mlc.yaml
new file mode 100644
index 0000000000000..acc430db5244e
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/nxp,lpc3220-mlc.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/nxp,lpc3220-mlc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP LPC32xx SoC NAND MLC controller
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+properties:
+ compatible:
+ const: nxp,lpc3220-mlc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ gpios:
+ maxItems: 1
+ description: GPIO specification for NAND write protect
+
+ nxp,tcea-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: TCEA_DELAY in Hz
+
+ nxp,busy-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: BUSY_DELAY in Hz
+
+ nxp,nand-ta:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: NAND_TA in Hz
+
+ nxp,rd-high:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: RD_HIGH in Hz
+
+ nxp,rd-low:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: RD_LOW in Hz
+
+ nxp,wr-high:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: WR_HIGH in Hz
+
+ nxp,wr-low:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: WR_LOW in Hz
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - gpios
+
+allOf:
+ - $ref: nand-controller.yaml
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ nand-controller@200a8000 {
+ compatible = "nxp,lpc3220-mlc";
+ reg = <0x200A8000 0x11000>;
+ interrupts = <11 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nxp,tcea-delay = <333333333>;
+ nxp,busy-delay = <10000000>;
+ nxp,nand-ta = <18181818>;
+ nxp,rd-high = <31250000>;
+ nxp,rd-low = <45454545>;
+ nxp,wr-high = <40000000>;
+ nxp,wr-low = <83333333>;
+ gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH 1/1] dt-bindings: mtd: convert lpc32xx-mlc.txt to yaml format
2025-06-23 20:26 [PATCH 1/1] dt-bindings: mtd: convert lpc32xx-mlc.txt to yaml format Frank Li
@ 2025-06-27 2:52 ` Rob Herring
0 siblings, 0 replies; 2+ messages in thread
From: Rob Herring @ 2025-06-27 2:52 UTC (permalink / raw)
To: Frank Li
Cc: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Krzysztof Kozlowski, Conor Dooley, Vladimir Zapolskiy,
Piotr Wojtaszczyk, open list:MEMORY TECHNOLOGY DEVICES (MTD),
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/LPC32XX SOC SUPPORT, open list, imx
On Mon, Jun 23, 2025 at 04:26:42PM -0400, Frank Li wrote:
> Convert lpc32xx-mlc.txt to yaml format.
>
> Additional changes:
> - add ref to nand-controller.yaml.
> - replace _ with - in property names.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> .../devicetree/bindings/mtd/lpc32xx-mlc.txt | 50 ------------
> .../bindings/mtd/nxp,lpc3220-mlc.yaml | 81 +++++++++++++++++++
> 2 files changed, 81 insertions(+), 50 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt
> create mode 100644 Documentation/devicetree/bindings/mtd/nxp,lpc3220-mlc.yaml
>
> diff --git a/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt b/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt
> deleted file mode 100644
> index 64c06aa05ac71..0000000000000
> --- a/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt
> +++ /dev/null
> @@ -1,50 +0,0 @@
> -NXP LPC32xx SoC NAND MLC controller
> -
> -Required properties:
> -- compatible: "nxp,lpc3220-mlc"
> -- reg: Address and size of the controller
> -- interrupts: The NAND interrupt specification
> -- gpios: GPIO specification for NAND write protect
> -
> -The following required properties are very controller specific. See the LPC32xx
> -User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
> -Hz, to make them independent of actual clock speed and to provide for good
> -accuracy:)
> -- nxp,tcea_delay: TCEA_DELAY
> -- nxp,busy_delay: BUSY_DELAY
> -- nxp,nand_ta: NAND_TA
> -- nxp,rd_high: RD_HIGH
> -- nxp,rd_low: RD_LOW
> -- nxp,wr_high: WR_HIGH
> -- nxp,wr_low: WR_LOW
> -
> -Optional subnodes:
> -- Partitions, see Documentation/devicetree/bindings/mtd/mtd.yaml
> -
> -Example:
> -
> - mlc: flash@200a8000 {
> - compatible = "nxp,lpc3220-mlc";
> - reg = <0x200A8000 0x11000>;
> - interrupts = <11 0>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> -
> - nxp,tcea-delay = <333333333>;
> - nxp,busy-delay = <10000000>;
> - nxp,nand-ta = <18181818>;
> - nxp,rd-high = <31250000>;
> - nxp,rd-low = <45454545>;
> - nxp,wr-high = <40000000>;
> - nxp,wr-low = <83333333>;
> - gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
> -
> - mtd0@00000000 {
> - label = "boot";
> - reg = <0x00000000 0x00064000>;
> - read-only;
> - };
> -
> - ...
> -
> - };
> diff --git a/Documentation/devicetree/bindings/mtd/nxp,lpc3220-mlc.yaml b/Documentation/devicetree/bindings/mtd/nxp,lpc3220-mlc.yaml
> new file mode 100644
> index 0000000000000..acc430db5244e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/nxp,lpc3220-mlc.yaml
> @@ -0,0 +1,81 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/nxp,lpc3220-mlc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP LPC32xx SoC NAND MLC controller
> +
> +maintainers:
> + - Frank Li <Frank.Li@nxp.com>
> +
> +properties:
> + compatible:
> + const: nxp,lpc3220-mlc
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + gpios:
> + maxItems: 1
> + description: GPIO specification for NAND write protect
> +
> + nxp,tcea-delay:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: TCEA_DELAY in Hz
> +
> + nxp,busy-delay:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: BUSY_DELAY in Hz
> +
> + nxp,nand-ta:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: NAND_TA in Hz
> +
> + nxp,rd-high:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: RD_HIGH in Hz
> +
> + nxp,rd-low:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: RD_LOW in Hz
> +
> + nxp,wr-high:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: WR_HIGH in Hz
> +
> + nxp,wr-low:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: WR_LOW in Hz
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - gpios
> +
> +allOf:
> + - $ref: nand-controller.yaml
Do either of these use this? They don't define 'nand' chip nodes, do
they?
No partitions on this one?
Rob
^ permalink raw reply [flat|nested] 2+ messages in thread
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