Re: [PATCH 4/5] clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR

Alexander Stein
2025-07-01T09:51:12Z

Hi,

thanks for the patch.

Am Dienstag, 1. Juli 2025, 09:04:40 CEST schrieb Peng Fan:
> i.MX94 BLK CTL LVDS CSR's LVDS_PHY_CLOCK_CONTRL register controls the clock
> gating logic of LVDS units. Display CSR's DISPLAY_ENGINES_CLOCK_CONTROL
> register controls the selection of the clock feeding the display engine.
>
> Add clock gate support for the two CSRs.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/clk/imx/clk-imx95-blk-ctl.c | 50 ++++++++++++++++++++++++++++++++++++-
> 1 file changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
> index 828ee0a81ff62c6e4f61eef350b9073f19f5351f..5fe582b0d4a9a197f2c1a49dc18f15ca83ccb4a4 100644
> --- a/drivers/clk/imx/clk-imx95-blk-ctl.c
> +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
> @@ -1,8 +1,9 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright 2024 NXP
> + * Copyright 2024-2025 NXP
> */
>
> +#include <dt-bindings/clock/nxp,imx94-clock.h>
> #include <dt-bindings/clock/nxp,imx95-clock.h>
> #include <linux/clk.h>
> #include <linux/clk-provider.h>
> @@ -300,6 +301,51 @@ static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {
> .clk_reg_offset = 0,
> };
>
> +static const struct imx95_blk_ctl_clk_dev_data imx94_lvds_clk_dev_data[] = {
> + [IMX94_CLK_DISPMIX_LVDS_CLK_GATE] = {
> + .name = "lvds_clk_gate",
> + .parent_names = (const char *[]){ "ldbpll", },
> + .num_parents = 1,
> + .reg = 0,
> + .bit_idx = 1,
> + .bit_width = 1,
> + .type = CLK_GATE,
> + .flags = CLK_SET_RATE_PARENT,
> + .flags2 = CLK_GATE_SET_TO_DISABLE,
> + },
> +};
> +
> +static const struct imx95_blk_ctl_dev_data imx94_lvds_csr_dev_data = {
> + .num_clks = ARRAY_SIZE(imx94_lvds_clk_dev_data),
> + .clk_dev_data = imx94_lvds_clk_dev_data,
> + .clk_reg_offset = 0,
> + .rpm_enabled = true,
> +};
> +
> +static const char * const imx94_disp_engine_parents[] = {
> + "disppix", "ldb_pll_div7"
> +};
> +
> +static const struct imx95_blk_ctl_clk_dev_data imx94_dispmix_csr_clk_dev_data[] = {
> + [IMX94_CLK_DISPMIX_CLK_SEL] = {
> + .name = "disp_clk_sel",
> + .parent_names = imx94_disp_engine_parents,
> + .num_parents = ARRAY_SIZE(imx94_disp_engine_parents),
> + .reg = 0,
> + .bit_idx = 1,
> + .bit_width = 1,
> + .type = CLK_MUX,
> + .flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const struct imx95_blk_ctl_dev_data imx94_dispmix_csr_dev_data = {
> + .num_clks = ARRAY_SIZE(imx94_dispmix_csr_clk_dev_data),
> + .clk_dev_data = imx94_dispmix_csr_clk_dev_data,
> + .clk_reg_offset = 0,
> + .rpm_enabled = true,
> +};
> +
> static int imx95_bc_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -474,6 +520,8 @@ static const struct of_device_id imx95_bc_of_match[] = {
> { .compatible = "nxp,imx95-hsio-blk-ctl", .data = &hsio_blk_ctl_dev_data },
> { .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
> { .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},
> + { .compatible = "nxp,imx94-lvds-csr", .data = &imx94_lvds_csr_dev_data },
> + { .compatible = "nxp,imx94-display-csr", .data = &imx94_dispmix_csr_dev_data },

Similar to patch 1, sort them properly.

Best regards,
Alexander

> { /* Sentinel */ },
> };
> MODULE_DEVICE_TABLE(of, imx95_bc_of_match);
>
>

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