* [PATCH v3 1/5] dt-bindings: arm: sunxi: Add NetCube Systems Nagami SoM and carrier board bindings
2025-07-07 18:44 [PATCH v3 0/5] Add support for NetCube Systems Nagami SoM and its carrier boards Lukas Schmid
@ 2025-07-07 18:44 ` Lukas Schmid
2025-07-07 18:44 ` [PATCH v3 2/5] riscv: dts: allwinner: d1s-t113: Add pinctrl's required by NetCube Systems Nagami SoM Lukas Schmid
` (3 subsequent siblings)
4 siblings, 0 replies; 12+ messages in thread
From: Lukas Schmid @ 2025-07-07 18:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Maxime Ripard
Cc: Lukas Schmid, Krzysztof Kozlowski, devicetree, linux-arm-kernel,
linux-sunxi, linux-kernel, linux-riscv
The NetCube Systems Nagami is an System on Module base on the Allwinner
T113s SoC. It is intended to be used in low cost devices which require
simple layouts and low BOM cost.
The NetCube Systems Nagami Basic Carrier Board is a simple carrier for the
Nagami SoM. It is intended to serve as a simple reference design for a
custom implementation or just evaluating the module with other peripherals
The NetCube Systems Nagami Keypad Carrier is a custom board intended to
fit a standard Ritto Intercom enclosure and provides a Keypad, NFC-Reader
and Status-LED all controllable over Ethernet with PoE support.
Signed-off-by: Lukas Schmid <lukas.schmid@netcube.li>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/arm/sunxi.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
index 7807ea613..50f08d8d2 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
@@ -599,6 +599,14 @@ properties:
- const: netcube,kumquat
- const: allwinner,sun8i-v3s
+ - description: NetCube Systems Nagami SoM based boards
+ items:
+ - enum:
+ - netcube,nagami-basic-carrier
+ - netcube,nagami-keypad-carrier
+ - const: netcube,nagami
+ - const: allwinner,sun8i-t113s
+
- description: NextThing Co. CHIP
items:
- const: nextthing,chip
--
2.39.5
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v3 2/5] riscv: dts: allwinner: d1s-t113: Add pinctrl's required by NetCube Systems Nagami SoM
2025-07-07 18:44 [PATCH v3 0/5] Add support for NetCube Systems Nagami SoM and its carrier boards Lukas Schmid
2025-07-07 18:44 ` [PATCH v3 1/5] dt-bindings: arm: sunxi: Add NetCube Systems Nagami SoM and carrier board bindings Lukas Schmid
@ 2025-07-07 18:44 ` Lukas Schmid
2025-07-08 16:36 ` Chen-Yu Tsai
2025-07-07 18:44 ` [PATCH v3 3/5] ARM: dts: sunxi: add support for " Lukas Schmid
` (2 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Lukas Schmid @ 2025-07-07 18:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Maxime Ripard
Cc: Lukas Schmid, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-riscv
Added the following pinctrl's used by the NetCube Systems Nagami SoM
* i2c2_pins
* i2c3_pins
* i2s1_pins, i2s1_din_pins, i2s1_dout_pins
* spi1_pins
Signed-off-by: Lukas Schmid <lukas.schmid@netcube.li>
---
.../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
index e4175adb0..8dc3deccb 100644
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -78,6 +78,36 @@ dsi_4lane_pins: dsi-4lane-pins {
function = "dsi";
};
+ /omit-if-no-ref/
+ i2c2_pins: i2c2-pins {
+ pins = "PD20", "PD21";
+ function = "i2c2";
+ };
+
+ /omit-if-no-ref/
+ i2c3_pins: i2c3-pins {
+ pins = "PG10", "PG11";
+ function = "i2c3";
+ };
+
+ /omit-if-no-ref/
+ i2s1_pins: i2s1-pins {
+ pins = "PG12", "PG13";
+ function = "i2s1";
+ };
+
+ /omit-if-no-ref/
+ i2s1_din_pins: i2s1-din-pins {
+ pins = "PG14";
+ function = "i2s1_din";
+ };
+
+ /omit-if-no-ref/
+ i2s1_dout_pins: i2s1-dout-pins {
+ pins = "PG15";
+ function = "i2s1_dout";
+ };
+
/omit-if-no-ref/
lcd_rgb666_pins: lcd-rgb666-pins {
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
@@ -126,6 +156,12 @@ spi0_pins: spi0-pins {
function = "spi0";
};
+ /omit-if-no-ref/
+ spi1_pins: spi1-pins {
+ pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15";
+ function = "spi1";
+ };
+
/omit-if-no-ref/
uart1_pg6_pins: uart1-pg6-pins {
pins = "PG6", "PG7";
--
2.39.5
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v3 2/5] riscv: dts: allwinner: d1s-t113: Add pinctrl's required by NetCube Systems Nagami SoM
2025-07-07 18:44 ` [PATCH v3 2/5] riscv: dts: allwinner: d1s-t113: Add pinctrl's required by NetCube Systems Nagami SoM Lukas Schmid
@ 2025-07-08 16:36 ` Chen-Yu Tsai
2025-07-08 16:39 ` Lukas Schmid
0 siblings, 1 reply; 12+ messages in thread
From: Chen-Yu Tsai @ 2025-07-08 16:36 UTC (permalink / raw)
To: Lukas Schmid
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jernej Skrabec,
Samuel Holland, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Maxime Ripard, devicetree, linux-arm-kernel,
linux-sunxi, linux-kernel, linux-riscv
On Tue, Jul 8, 2025 at 8:35 AM Lukas Schmid <lukas.schmid@netcube.li> wrote:
>
> Added the following pinctrl's used by the NetCube Systems Nagami SoM
> * i2c2_pins
> * i2c3_pins
> * i2s1_pins, i2s1_din_pins, i2s1_dout_pins
> * spi1_pins
>
> Signed-off-by: Lukas Schmid <lukas.schmid@netcube.li>
> ---
> .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 36 +++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> index e4175adb0..8dc3deccb 100644
> --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> @@ -78,6 +78,36 @@ dsi_4lane_pins: dsi-4lane-pins {
> function = "dsi";
> };
>
> + /omit-if-no-ref/
> + i2c2_pins: i2c2-pins {
> + pins = "PD20", "PD21";
> + function = "i2c2";
> + };
> +
> + /omit-if-no-ref/
> + i2c3_pins: i2c3-pins {
> + pins = "PG10", "PG11";
> + function = "i2c3";
> + };
> +
> + /omit-if-no-ref/
> + i2s1_pins: i2s1-pins {
> + pins = "PG12", "PG13";
> + function = "i2s1";
> + };
> +
> + /omit-if-no-ref/
> + i2s1_din_pins: i2s1-din-pins {
> + pins = "PG14";
> + function = "i2s1_din";
> + };
> +
> + /omit-if-no-ref/
> + i2s1_dout_pins: i2s1-dout-pins {
> + pins = "PG15";
> + function = "i2s1_dout";
> + };
> +
> /omit-if-no-ref/
> lcd_rgb666_pins: lcd-rgb666-pins {
> pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
> @@ -126,6 +156,12 @@ spi0_pins: spi0-pins {
> function = "spi0";
> };
>
> + /omit-if-no-ref/
> + spi1_pins: spi1-pins {
> + pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15";
Could you split out the WP and HOLD pins as separate nodes. They aren't
strictly needed for SPI, and folks might have designs that use the two
pins for other purposes.
Thanks
ChenYu
> + function = "spi1";
> + };
> +
> /omit-if-no-ref/
> uart1_pg6_pins: uart1-pg6-pins {
> pins = "PG6", "PG7";
> --
> 2.39.5
>
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 2/5] riscv: dts: allwinner: d1s-t113: Add pinctrl's required by NetCube Systems Nagami SoM
2025-07-08 16:36 ` Chen-Yu Tsai
@ 2025-07-08 16:39 ` Lukas Schmid
0 siblings, 0 replies; 12+ messages in thread
From: Lukas Schmid @ 2025-07-08 16:39 UTC (permalink / raw)
To: wens
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jernej Skrabec,
Samuel Holland, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Maxime Ripard, devicetree, linux-arm-kernel,
linux-sunxi, linux-kernel, linux-riscv
[-- Attachment #1: Type: text/plain, Size: 3537 bytes --]
On Dienstag, 8. Juli 2025 18:36:03 CEST Chen-Yu Tsai wrote:
> On Tue, Jul 8, 2025 at 8:35 AM Lukas Schmid <lukas.schmid@netcube.li> wrote:
> > Added the following pinctrl's used by the NetCube Systems Nagami SoM
> >
> > * i2c2_pins
> > * i2c3_pins
> > * i2s1_pins, i2s1_din_pins, i2s1_dout_pins
> > * spi1_pins
> >
> > Signed-off-by: Lukas Schmid <lukas.schmid@netcube.li>
> > ---
> >
> > .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 36 +++++++++++++++++++
> > 1 file changed, 36 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index
> > e4175adb0..8dc3deccb 100644
> > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > @@ -78,6 +78,36 @@ dsi_4lane_pins: dsi-4lane-pins {
> >
> > function = "dsi";
> >
> > };
> >
> > + /omit-if-no-ref/
> > + i2c2_pins: i2c2-pins {
> > + pins = "PD20", "PD21";
> > + function = "i2c2";
> > + };
> > +
> > + /omit-if-no-ref/
> > + i2c3_pins: i2c3-pins {
> > + pins = "PG10", "PG11";
> > + function = "i2c3";
> > + };
> > +
> > + /omit-if-no-ref/
> > + i2s1_pins: i2s1-pins {
> > + pins = "PG12", "PG13";
> > + function = "i2s1";
> > + };
> > +
> > + /omit-if-no-ref/
> > + i2s1_din_pins: i2s1-din-pins {
> > + pins = "PG14";
> > + function = "i2s1_din";
> > + };
> > +
> > + /omit-if-no-ref/
> > + i2s1_dout_pins: i2s1-dout-pins {
> > + pins = "PG15";
> > + function = "i2s1_dout";
> > + };
> > +
> >
> > /omit-if-no-ref/
> > lcd_rgb666_pins: lcd-rgb666-pins {
> >
> > pins = "PD0", "PD1", "PD2", "PD3", "PD4",
> > "PD5",
> >
> > @@ -126,6 +156,12 @@ spi0_pins: spi0-pins {
> >
> > function = "spi0";
> >
> > };
> >
> > + /omit-if-no-ref/
> > + spi1_pins: spi1-pins {
> > + pins = "PD10", "PD11", "PD12", "PD13",
> > "PD14", "PD15";
> Could you split out the WP and HOLD pins as separate nodes. They aren't
> strictly needed for SPI, and folks might have designs that use the two
> pins for other purposes.
>
Sure. Do you want them as seperate ones, or is "spi1_hold_wp_pins" fine?
>
> Thanks
> ChenYu
>
> > + function = "spi1";
> > + };
> > +
> >
> > /omit-if-no-ref/
> > uart1_pg6_pins: uart1-pg6-pins {
> >
> > pins = "PG6", "PG7";
> >
> > --
> > 2.39.5
[-- Attachment #2: This is a digitally signed message part. --]
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 3/5] ARM: dts: sunxi: add support for NetCube Systems Nagami SoM
2025-07-07 18:44 [PATCH v3 0/5] Add support for NetCube Systems Nagami SoM and its carrier boards Lukas Schmid
2025-07-07 18:44 ` [PATCH v3 1/5] dt-bindings: arm: sunxi: Add NetCube Systems Nagami SoM and carrier board bindings Lukas Schmid
2025-07-07 18:44 ` [PATCH v3 2/5] riscv: dts: allwinner: d1s-t113: Add pinctrl's required by NetCube Systems Nagami SoM Lukas Schmid
@ 2025-07-07 18:44 ` Lukas Schmid
2025-07-07 23:22 ` Andre Przywara
2025-07-07 18:44 ` [PATCH v3 4/5] ARM: dts: sunxi: add support for NetCube Systems Nagami Basic Carrier Lukas Schmid
2025-07-07 18:44 ` [PATCH v3 5/5] ARM: dts: sunxi: add support for NetCube Systems Nagami Keypad Carrier Lukas Schmid
4 siblings, 1 reply; 12+ messages in thread
From: Lukas Schmid @ 2025-07-07 18:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Maxime Ripard
Cc: Lukas Schmid, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-riscv
NetCube Systems Nagami SoM is a module based around the Allwinner T113s
SoC. It includes the following features and interfaces:
- 128MB DDR3 included in SoC
- 10/100 Mbps Ethernet using LAN8720A phy
- One USB-OTG interface
- One USB-Host interface
- One I2S interface with in and output support
- Two CAN interfaces
- ESP32 over SDIO
- One SPI interface
- I2C EEPROM for MAC address
- One QWIIC I2C Interface with dedicated interrupt pin shared with EEPROM
- One external I2C interface
- SD interface for external SD-Card
Signed-off-by: Lukas Schmid <lukas.schmid@netcube.li>
---
.../allwinner/sun8i-t113s-netcube-nagami.dtsi | 233 ++++++++++++++++++
1 file changed, 233 insertions(+)
create mode 100644 arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi
diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi
new file mode 100644
index 000000000..0db867b47
--- /dev/null
+++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2025 Lukas Schmid <lukas.schmid@netcube.li>
+ */
+
+/dts-v1/;
+#include "sun8i-t113s.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "NetCube Systems Nagami SoM";
+ compatible = "netcube,nagami", "allwinner,sun8i-t113s";
+
+ aliases {
+ serial1 = &uart1; // ESP32 Bootloader UART
+ serial3 = &uart3; // Console UART on Card Edge
+ ethernet0 = &emac;
+ };
+
+ chosen {
+ stdout-path = "serial3:115200n8";
+ };
+
+ /* module wide 3.3V supply directly from the card edge */
+ reg_vcc3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */
+ reg_vcc_core: regulator-core {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-core";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ vin-supply = <®_vcc3v3>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_vcc_core>;
+};
+
+&cpu1 {
+ cpu-supply = <®_vcc_core>;
+};
+
+&dcxo {
+ clock-frequency = <24000000>;
+};
+
+&emac {
+ nvmem-cells = <ð0_macaddress>;
+ nvmem-cell-names = "mac-address";
+ phy-handle = <&lan8720a>;
+ phy-mode = "rmii";
+ pinctrl-0 = <&rmii_pe_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/* Exposed as I2C on the card edge */
+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+};
+
+/* Exposed as the QWIIC connector and used by the internal EEPROM */
+&i2c3 {
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ eeprom0: eeprom@50 {
+ compatible = "atmel,24c02"; /* actually it's a 24AA02E48 */
+ reg = <0x50>;
+ pagesize = <16>;
+ read-only;
+ vcc-supply = <®_vcc3v3>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eth0_macaddress: macaddress@fa {
+ reg = <0xfa 0x06>;
+ };
+ };
+};
+
+/* Exposed as I2S on the card edge */
+&i2s1 {
+ pinctrl-0 = <&i2s1_pins>, <&i2s1_din_pins>, <&i2s1_dout_pins>;
+ pinctrl-names = "default";
+};
+
+/* Phy is on SoM. MDI signals pre-magentics are on the card edge */
+&mdio {
+ lan8720a: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
+/* Exposed as SD on the card edge */
+&mmc0 {
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <®_vcc3v3>;
+ broken-cd;
+ disable-wp;
+ bus-width = <4>;
+};
+
+/* Connected to the on-board ESP32 */
+&mmc1 {
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+/* Connected to the on-board eMMC */
+&mmc2 {
+ pinctrl-0 = <&mmc2_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&pio {
+ vcc-pb-supply = <®_vcc3v3>;
+ vcc-pc-supply = <®_vcc3v3>;
+ vcc-pd-supply = <®_vcc3v3>;
+ vcc-pe-supply = <®_vcc3v3>;
+ vcc-pf-supply = <®_vcc3v3>;
+ vcc-pg-supply = <®_vcc3v3>;
+
+ gpio-line-names = "", "", "", "", // PA
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "CAN0_TX", "CAN0_RX", // PB
+ "CAN1_TX", "CAN1_RX", "UART3_TX", "UART3_RX",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "eMMC_CLK", "eMMC_CMD", // PC
+ "eMMC_D2", "eMMC_D1", "eMMC_D0", "eMMC_D3",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "", // PD
+ "", "", "", "",
+ "", "", "SPI1_CS", "SPI1_CLK",
+ "SPI1_MOSI", "SPI1_MISO", "SPI1_HOLD", "SPI1_WP",
+ "PD16", "", "", "",
+ "I2C2_SCL", "I2C2_SDA", "PD22", "",
+ "", "", "", "",
+ "", "", "", "",
+ "ETH_CRSDV", "ETH_RXD0", "ETH_RXD1", "ETH_TXCK", // PE
+ "ETH_TXD0", "ETH_TXD1", "ETH_TXEN", "",
+ "ETH_MDC", "ETH_MDIO", "QWIIC_nINT", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "SD_D1", "SD_D0", "SD_CLK", "SD_CLK", // PF
+ "SD_D3", "SD_D2", "PF6", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "ESP_CLK", "ESP_CMD", "ESP_D0", "ESP_D1", // PG
+ "ESP_D2", "ESP_D3", "UART1_TXD", "UART1_RXD",
+ "ESP_nBOOT", "ESP_nRST", "I2C3_SCL", "I2C3_SDA",
+ "I2S1_WS", "I2S1_CLK", "I2S1_DIN0", "I2S1_DOUT0",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+/* Remove the unused CK pin from the pinctl as it is unconnected */
+&rmii_pe_pins {
+ pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+ "PE5", "PE6", "PE8", "PE9";
+};
+
+/* Exposed as SPI on the card-edge */
+&spi1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&spi1_pins>;
+ pinctrl-names = "default";
+ cs-gpios = <0>;
+};
+
+/* Connected to the Bootloader/Console of the ESP32 */
+&uart1 {
+ pinctrl-0 = <&uart1_pg6_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/* Exposed as the Console/Debug UART on the card-edge */
+&uart3 {
+ pinctrl-0 = <&uart3_pb_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--
2.39.5
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v3 3/5] ARM: dts: sunxi: add support for NetCube Systems Nagami SoM
2025-07-07 18:44 ` [PATCH v3 3/5] ARM: dts: sunxi: add support for " Lukas Schmid
@ 2025-07-07 23:22 ` Andre Przywara
2025-07-08 15:19 ` Lukas Schmid
0 siblings, 1 reply; 12+ messages in thread
From: Andre Przywara @ 2025-07-07 23:22 UTC (permalink / raw)
To: Lukas Schmid
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Maxime Ripard, devicetree,
linux-arm-kernel, linux-sunxi, linux-kernel, linux-riscv
On Mon, 7 Jul 2025 20:44:15 +0200
Lukas Schmid <lukas.schmid@netcube.li> wrote:
Hi Lukas,
please try to refrain from sending subsequent patches too quickly, that
might just put off and confuse reviewers. To acknowledge a change
request, it is probably sufficient to just reply to the mail with a
confirmation.
> NetCube Systems Nagami SoM is a module based around the Allwinner T113s
> SoC. It includes the following features and interfaces:
>
> - 128MB DDR3 included in SoC
> - 10/100 Mbps Ethernet using LAN8720A phy
> - One USB-OTG interface
> - One USB-Host interface
> - One I2S interface with in and output support
> - Two CAN interfaces
> - ESP32 over SDIO
> - One SPI interface
> - I2C EEPROM for MAC address
> - One QWIIC I2C Interface with dedicated interrupt pin shared with EEPROM
> - One external I2C interface
> - SD interface for external SD-Card
>
> Signed-off-by: Lukas Schmid <lukas.schmid@netcube.li>
> ---
> .../allwinner/sun8i-t113s-netcube-nagami.dtsi | 233 ++++++++++++++++++
> 1 file changed, 233 insertions(+)
> create mode 100644 arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi
>
> diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi
> new file mode 100644
> index 000000000..0db867b47
> --- /dev/null
> +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi
> @@ -0,0 +1,233 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2025 Lukas Schmid <lukas.schmid@netcube.li>
> + */
> +
> +/dts-v1/;
> +#include "sun8i-t113s.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + model = "NetCube Systems Nagami SoM";
> + compatible = "netcube,nagami", "allwinner,sun8i-t113s";
> +
> + aliases {
> + serial1 = &uart1; // ESP32 Bootloader UART
> + serial3 = &uart3; // Console UART on Card Edge
> + ethernet0 = &emac;
> + };
> +
> + chosen {
> + stdout-path = "serial3:115200n8";
> + };
> +
> + /* module wide 3.3V supply directly from the card edge */
> + reg_vcc3v3: regulator-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc-3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */
> + reg_vcc_core: regulator-core {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc-core";
> + regulator-min-microvolt = <880000>;
> + regulator-max-microvolt = <880000>;
> + vin-supply = <®_vcc3v3>;
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <®_vcc_core>;
> +};
> +
> +&cpu1 {
> + cpu-supply = <®_vcc_core>;
> +};
> +
> +&dcxo {
> + clock-frequency = <24000000>;
> +};
> +
> +&emac {
> + nvmem-cells = <ð0_macaddress>;
> + nvmem-cell-names = "mac-address";
> + phy-handle = <&lan8720a>;
> + phy-mode = "rmii";
> + pinctrl-0 = <&rmii_pe_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +/* Exposed as I2C on the card edge */
> +&i2c2 {
> + pinctrl-0 = <&i2c2_pins>;
> + pinctrl-names = "default";
I wonder if this belongs here. In general we don't describe
pins/devices that are on generic connectors (like pin headers), because
the connection is determined by the user, not by the board.
In this case PD20 and PD21 could be used as generic GPIOs or as PWMs.
IIUC, even for the basic carrier those pins end up on headers, so even
there I wouldn't describe it. On the keypad carrier it's of course a
different story, since the MCP23008 is apparently soldered there.
> +};
> +
> +/* Exposed as the QWIIC connector and used by the internal EEPROM */
> +&i2c3 {
> + pinctrl-0 = <&i2c3_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + eeprom0: eeprom@50 {
> + compatible = "atmel,24c02"; /* actually it's a 24AA02E48 */
> + reg = <0x50>;
> + pagesize = <16>;
> + read-only;
> + vcc-supply = <®_vcc3v3>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + eth0_macaddress: macaddress@fa {
> + reg = <0xfa 0x06>;
> + };
> + };
> +};
> +
> +/* Exposed as I2S on the card edge */
> +&i2s1 {
> + pinctrl-0 = <&i2s1_pins>, <&i2s1_din_pins>, <&i2s1_dout_pins>;
> + pinctrl-names = "default";
Same story here, what prevents a user from using those edge pins as
GPIO or PWM?
> +};
> +
> +/* Phy is on SoM. MDI signals pre-magentics are on the card edge */
> +&mdio {
> + lan8720a: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + };
> +};
> +
> +/* Exposed as SD on the card edge */
> +&mmc0 {
> + pinctrl-0 = <&mmc0_pins>;
> + pinctrl-names = "default";
> + vmmc-supply = <®_vcc3v3>;
> + broken-cd;
> + disable-wp;
> + bus-width = <4>;
> +};
I think this node doesn't belong into the SoM .dtsi, as many details
are not set here, but on the carrier board: card detect, write protect,
Vmmc supply, and even bus width (could be 1 as well). So please move
this node to where the SD card connector sits. You might want to keep
the pinctrl nodes in here.
> +
> +/* Connected to the on-board ESP32 */
> +&mmc1 {
> + pinctrl-0 = <&mmc1_pins>;
> + pinctrl-names = "default";
> + vmmc-supply = <®_vcc3v3>;
> + bus-width = <4>;
> + non-removable;
> + status = "okay";
> +};
> +
> +/* Connected to the on-board eMMC */
> +&mmc2 {
> + pinctrl-0 = <&mmc2_pins>;
> + pinctrl-names = "default";
> + vmmc-supply = <®_vcc3v3>;
> + vqmmc-supply = <®_vcc3v3>;
> + bus-width = <4>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&pio {
> + vcc-pb-supply = <®_vcc3v3>;
> + vcc-pc-supply = <®_vcc3v3>;
> + vcc-pd-supply = <®_vcc3v3>;
> + vcc-pe-supply = <®_vcc3v3>;
> + vcc-pf-supply = <®_vcc3v3>;
> + vcc-pg-supply = <®_vcc3v3>;
> +
> + gpio-line-names = "", "", "", "", // PA
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "CAN0_TX", "CAN0_RX", // PB
> + "CAN1_TX", "CAN1_RX", "UART3_TX", "UART3_RX",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "eMMC_CLK", "eMMC_CMD", // PC
> + "eMMC_D2", "eMMC_D1", "eMMC_D0", "eMMC_D3",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "", // PD
> + "", "", "", "",
> + "", "", "SPI1_CS", "SPI1_CLK",
> + "SPI1_MOSI", "SPI1_MISO", "SPI1_HOLD", "SPI1_WP",
> + "PD16", "", "", "",
> + "I2C2_SCL", "I2C2_SDA", "PD22", "",
> + "", "", "", "",
> + "", "", "", "",
> + "ETH_CRSDV", "ETH_RXD0", "ETH_RXD1", "ETH_TXCK", // PE
> + "ETH_TXD0", "ETH_TXD1", "ETH_TXEN", "",
> + "ETH_MDC", "ETH_MDIO", "QWIIC_nINT", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "SD_D1", "SD_D0", "SD_CLK", "SD_CLK", // PF
> + "SD_D3", "SD_D2", "PF6", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "ESP_CLK", "ESP_CMD", "ESP_D0", "ESP_D1", // PG
> + "ESP_D2", "ESP_D3", "UART1_TXD", "UART1_RXD",
> + "ESP_nBOOT", "ESP_nRST", "I2C3_SCL", "I2C3_SDA",
> + "I2S1_WS", "I2S1_CLK", "I2S1_DIN0", "I2S1_DOUT0",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "";
> +};
> +
> +/* Remove the unused CK pin from the pinctl as it is unconnected */
> +&rmii_pe_pins {
> + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
> + "PE5", "PE6", "PE8", "PE9";
> +};
> +
> +/* Exposed as SPI on the card-edge */
> +&spi1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-0 = <&spi1_pins>;
> + pinctrl-names = "default";
> + cs-gpios = <0>;
> +};
I wonder if this belongs here as well, since it's again just generic
edge pins.
Cheers,
Andre
> +
> +/* Connected to the Bootloader/Console of the ESP32 */
> +&uart1 {
> + pinctrl-0 = <&uart1_pg6_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +/* Exposed as the Console/Debug UART on the card-edge */
> +&uart3 {
> + pinctrl-0 = <&uart3_pb_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 3/5] ARM: dts: sunxi: add support for NetCube Systems Nagami SoM
2025-07-07 23:22 ` Andre Przywara
@ 2025-07-08 15:19 ` Lukas Schmid
2025-07-08 15:35 ` Chen-Yu Tsai
2025-07-08 16:39 ` Andrew Lunn
0 siblings, 2 replies; 12+ messages in thread
From: Lukas Schmid @ 2025-07-08 15:19 UTC (permalink / raw)
To: Andre Przywara
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Maxime Ripard, devicetree,
linux-arm-kernel, linux-sunxi, linux-kernel, linux-riscv
[-- Attachment #1: Type: text/plain, Size: 10196 bytes --]
On Dienstag, 8. Juli 2025 01:22:05 CEST Andre Przywara wrote:
> On Mon, 7 Jul 2025 20:44:15 +0200
> Lukas Schmid <lukas.schmid@netcube.li> wrote:
>
Hi Andre,
> Hi Lukas,
>
> please try to refrain from sending subsequent patches too quickly, that
> might just put off and confuse reviewers. To acknowledge a change
> request, it is probably sufficient to just reply to the mail with a
> confirmation.
Sorry about that. I'm still trying to get the hang of this whole "submitting
patches" thing. What is a good time/reason to send the next revision/version
of a patchset?
>
> > NetCube Systems Nagami SoM is a module based around the Allwinner T113s
> > SoC. It includes the following features and interfaces:
> >
> > - 128MB DDR3 included in SoC
> > - 10/100 Mbps Ethernet using LAN8720A phy
> > - One USB-OTG interface
> > - One USB-Host interface
> > - One I2S interface with in and output support
> > - Two CAN interfaces
> > - ESP32 over SDIO
> > - One SPI interface
> > - I2C EEPROM for MAC address
> > - One QWIIC I2C Interface with dedicated interrupt pin shared with EEPROM
> > - One external I2C interface
> > - SD interface for external SD-Card
> >
> > Signed-off-by: Lukas Schmid <lukas.schmid@netcube.li>
> > ---
> >
> > .../allwinner/sun8i-t113s-netcube-nagami.dtsi | 233 ++++++++++++++++++
> > 1 file changed, 233 insertions(+)
> > create mode 100644
> > arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi>
> > diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi
> > b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi new file
> > mode 100644
> > index 000000000..0db867b47
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi
> > @@ -0,0 +1,233 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright (C) 2025 Lukas Schmid <lukas.schmid@netcube.li>
> > + */
> > +
> > +/dts-v1/;
> > +#include "sun8i-t113s.dtsi"
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > + model = "NetCube Systems Nagami SoM";
> > + compatible = "netcube,nagami", "allwinner,sun8i-t113s";
> > +
> > + aliases {
> > + serial1 = &uart1; // ESP32 Bootloader UART
> > + serial3 = &uart3; // Console UART on Card Edge
> > + ethernet0 = &emac;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial3:115200n8";
> > + };
> > +
> > + /* module wide 3.3V supply directly from the card edge */
> > + reg_vcc3v3: regulator-3v3 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "vcc-3v3";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-always-on;
> > + };
> > +
> > + /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */
> > + reg_vcc_core: regulator-core {
> > + compatible = "regulator-fixed";
> > + regulator-name = "vcc-core";
> > + regulator-min-microvolt = <880000>;
> > + regulator-max-microvolt = <880000>;
> > + vin-supply = <®_vcc3v3>;
> > + };
> > +};
> > +
> > +&cpu0 {
> > + cpu-supply = <®_vcc_core>;
> > +};
> > +
> > +&cpu1 {
> > + cpu-supply = <®_vcc_core>;
> > +};
> > +
> > +&dcxo {
> > + clock-frequency = <24000000>;
> > +};
> > +
> > +&emac {
> > + nvmem-cells = <ð0_macaddress>;
> > + nvmem-cell-names = "mac-address";
> > + phy-handle = <&lan8720a>;
> > + phy-mode = "rmii";
> > + pinctrl-0 = <&rmii_pe_pins>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +};
> > +
> > +/* Exposed as I2C on the card edge */
> > +&i2c2 {
> > + pinctrl-0 = <&i2c2_pins>;
> > + pinctrl-names = "default";
>
> I wonder if this belongs here. In general we don't describe
> pins/devices that are on generic connectors (like pin headers), because
> the connection is determined by the user, not by the board.
> In this case PD20 and PD21 could be used as generic GPIOs or as PWMs.
> IIUC, even for the basic carrier those pins end up on headers, so even
> there I wouldn't describe it. On the keypad carrier it's of course a
> different story, since the MCP23008 is apparently soldered there.
I get that part. However the module's description (as of yet unreleased)
specifies those pins for this exact function as they are meant to be available
on our modules using the same connector but other CPU/SoC. The Module's state
that this is the default option but other function's can be reconfigured or
they can be used as IO.
If it's an issue I can remove those here, but I would still add them into the
basic carrier as, even though they are only pin header, they are marked with
the dedicated function of said pin. For example the headers there are
specifically for "SPI", "I2S", "I2C" and the SD-Card slot.
>
> > +};
> > +
> > +/* Exposed as the QWIIC connector and used by the internal EEPROM */
> > +&i2c3 {
> > + pinctrl-0 = <&i2c3_pins>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +
> > + eeprom0: eeprom@50 {
> > + compatible = "atmel,24c02"; /*
actually it's a 24AA02E48 */
> > + reg = <0x50>;
> > + pagesize = <16>;
> > + read-only;
> > + vcc-supply = <®_vcc3v3>;
> > +
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + eth0_macaddress: macaddress@fa {
> > + reg = <0xfa 0x06>;
> > + };
> > + };
> > +};
> > +
> > +/* Exposed as I2S on the card edge */
> > +&i2s1 {
> > + pinctrl-0 = <&i2s1_pins>, <&i2s1_din_pins>, <&i2s1_dout_pins>;
> > + pinctrl-names = "default";
>
> Same story here, what prevents a user from using those edge pins as
> GPIO or PWM?
>
> > +};
> > +
> > +/* Phy is on SoM. MDI signals pre-magentics are on the card edge */
> > +&mdio {
> > + lan8720a: ethernet-phy@0 {
> > + compatible = "ethernet-phy-ieee802.3-c22";
> > + reg = <0>;
> > + };
> > +};
> > +
> > +/* Exposed as SD on the card edge */
> > +&mmc0 {
> > + pinctrl-0 = <&mmc0_pins>;
> > + pinctrl-names = "default";
> > + vmmc-supply = <®_vcc3v3>;
> > + broken-cd;
> > + disable-wp;
> > + bus-width = <4>;
> > +};
>
> I think this node doesn't belong into the SoM .dtsi, as many details
> are not set here, but on the carrier board: card detect, write protect,
> Vmmc supply, and even bus width (could be 1 as well). So please move
> this node to where the SD card connector sits. You might want to keep
> the pinctrl nodes in here.
Totally agree here, I will move this definition to the basic carrier, as it's
currently the only one with the SD-Interface connected. However my question
from above about the default function still applies here.
>
> > +
> > +/* Connected to the on-board ESP32 */
> > +&mmc1 {
> > + pinctrl-0 = <&mmc1_pins>;
> > + pinctrl-names = "default";
> > + vmmc-supply = <®_vcc3v3>;
> > + bus-width = <4>;
> > + non-removable;
> > + status = "okay";
> > +};
> > +
> > +/* Connected to the on-board eMMC */
> > +&mmc2 {
> > + pinctrl-0 = <&mmc2_pins>;
> > + pinctrl-names = "default";
> > + vmmc-supply = <®_vcc3v3>;
> > + vqmmc-supply = <®_vcc3v3>;
> > + bus-width = <4>;
> > + non-removable;
> > + status = "okay";
> > +};
> > +
> > +&pio {
> > + vcc-pb-supply = <®_vcc3v3>;
> > + vcc-pc-supply = <®_vcc3v3>;
> > + vcc-pd-supply = <®_vcc3v3>;
> > + vcc-pe-supply = <®_vcc3v3>;
> > + vcc-pf-supply = <®_vcc3v3>;
> > + vcc-pg-supply = <®_vcc3v3>;
> > +
> > + gpio-line-names = "", "", "", "", // PA
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "CAN0_TX",
"CAN0_RX", // PB
> > + "CAN1_TX",
"CAN1_RX", "UART3_TX", "UART3_RX",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "eMMC_CLK",
"eMMC_CMD", // PC
> > + "eMMC_D2",
"eMMC_D1", "eMMC_D0", "eMMC_D3",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "", //
PD
> > + "", "", "", "",
> > + "", "", "SPI1_CS",
"SPI1_CLK",
> > + "SPI1_MOSI",
"SPI1_MISO", "SPI1_HOLD", "SPI1_WP",
> > + "PD16", "", "", "",
> > + "I2C2_SCL",
"I2C2_SDA", "PD22", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "ETH_CRSDV",
"ETH_RXD0", "ETH_RXD1", "ETH_TXCK", // PE
> > + "ETH_TXD0",
"ETH_TXD1", "ETH_TXEN", "",
> > + "ETH_MDC",
"ETH_MDIO", "QWIIC_nINT", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "SD_D1", "SD_D0",
"SD_CLK", "SD_CLK", // PF
> > + "SD_D3", "SD_D2",
"PF6", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "ESP_CLK",
"ESP_CMD", "ESP_D0", "ESP_D1", // PG
> > + "ESP_D2", "ESP_D3",
"UART1_TXD", "UART1_RXD",
> > + "ESP_nBOOT",
"ESP_nRST", "I2C3_SCL", "I2C3_SDA",
> > + "I2S1_WS",
"I2S1_CLK", "I2S1_DIN0", "I2S1_DOUT0",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "",
> > + "", "", "", "";
> > +};
> > +
> > +/* Remove the unused CK pin from the pinctl as it is unconnected */
> > +&rmii_pe_pins {
> > + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
> > + "PE5", "PE6", "PE8", "PE9";
> > +};
> > +
> > +/* Exposed as SPI on the card-edge */
> > +&spi1 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + pinctrl-0 = <&spi1_pins>;
> > + pinctrl-names = "default";
> > + cs-gpios = <0>;
> > +};
>
> I wonder if this belongs here as well, since it's again just generic
> edge pins.
Same here too
>
> Cheers,
> Andre
>
> > +
> > +/* Connected to the Bootloader/Console of the ESP32 */
> > +&uart1 {
> > + pinctrl-0 = <&uart1_pg6_pins>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +};
> > +
> > +/* Exposed as the Console/Debug UART on the card-edge */
> > +&uart3 {
> > + pinctrl-0 = <&uart3_pb_pins>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +};
[-- Attachment #2: This is a digitally signed message part. --]
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^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 3/5] ARM: dts: sunxi: add support for NetCube Systems Nagami SoM
2025-07-08 15:19 ` Lukas Schmid
@ 2025-07-08 15:35 ` Chen-Yu Tsai
2025-07-08 16:39 ` Andrew Lunn
1 sibling, 0 replies; 12+ messages in thread
From: Chen-Yu Tsai @ 2025-07-08 15:35 UTC (permalink / raw)
To: Lukas Schmid
Cc: Andre Przywara, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jernej Skrabec, Samuel Holland, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Maxime Ripard, devicetree,
linux-arm-kernel, linux-sunxi, linux-kernel, linux-riscv
Hi,
On Tue, Jul 8, 2025 at 11:19 PM Lukas Schmid <lukas.schmid@netcube.li> wrote:
>
> On Dienstag, 8. Juli 2025 01:22:05 CEST Andre Przywara wrote:
> > On Mon, 7 Jul 2025 20:44:15 +0200
> > Lukas Schmid <lukas.schmid@netcube.li> wrote:
> >
> Hi Andre,
>
> > Hi Lukas,
> >
> > please try to refrain from sending subsequent patches too quickly, that
> > might just put off and confuse reviewers. To acknowledge a change
> > request, it is probably sufficient to just reply to the mail with a
> > confirmation.
>
> Sorry about that. I'm still trying to get the hang of this whole "submitting
> patches" thing. What is a good time/reason to send the next revision/version
> of a patchset?
>
> >
> > > NetCube Systems Nagami SoM is a module based around the Allwinner T113s
> > > SoC. It includes the following features and interfaces:
> > >
> > > - 128MB DDR3 included in SoC
> > > - 10/100 Mbps Ethernet using LAN8720A phy
> > > - One USB-OTG interface
> > > - One USB-Host interface
> > > - One I2S interface with in and output support
> > > - Two CAN interfaces
> > > - ESP32 over SDIO
> > > - One SPI interface
> > > - I2C EEPROM for MAC address
> > > - One QWIIC I2C Interface with dedicated interrupt pin shared with EEPROM
> > > - One external I2C interface
> > > - SD interface for external SD-Card
> > >
> > > Signed-off-by: Lukas Schmid <lukas.schmid@netcube.li>
> > > ---
> > >
> > > .../allwinner/sun8i-t113s-netcube-nagami.dtsi | 233 ++++++++++++++++++
> > > 1 file changed, 233 insertions(+)
> > > create mode 100644
> > > arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi>
> > > diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi
> > > b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi new file
> > > mode 100644
> > > index 000000000..0db867b47
> > > --- /dev/null
> > > +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi
> > > @@ -0,0 +1,233 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > +/*
> > > + * Copyright (C) 2025 Lukas Schmid <lukas.schmid@netcube.li>
> > > + */
> > > +
> > > +/dts-v1/;
> > > +#include "sun8i-t113s.dtsi"
> > > +
> > > +#include <dt-bindings/gpio/gpio.h>
> > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > +
> > > +/ {
> > > + model = "NetCube Systems Nagami SoM";
> > > + compatible = "netcube,nagami", "allwinner,sun8i-t113s";
> > > +
> > > + aliases {
> > > + serial1 = &uart1; // ESP32 Bootloader UART
> > > + serial3 = &uart3; // Console UART on Card Edge
> > > + ethernet0 = &emac;
> > > + };
> > > +
> > > + chosen {
> > > + stdout-path = "serial3:115200n8";
> > > + };
> > > +
> > > + /* module wide 3.3V supply directly from the card edge */
> > > + reg_vcc3v3: regulator-3v3 {
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "vcc-3v3";
> > > + regulator-min-microvolt = <3300000>;
> > > + regulator-max-microvolt = <3300000>;
> > > + regulator-always-on;
> > > + };
> > > +
> > > + /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */
> > > + reg_vcc_core: regulator-core {
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "vcc-core";
> > > + regulator-min-microvolt = <880000>;
> > > + regulator-max-microvolt = <880000>;
> > > + vin-supply = <®_vcc3v3>;
> > > + };
> > > +};
> > > +
> > > +&cpu0 {
> > > + cpu-supply = <®_vcc_core>;
> > > +};
> > > +
> > > +&cpu1 {
> > > + cpu-supply = <®_vcc_core>;
> > > +};
> > > +
> > > +&dcxo {
> > > + clock-frequency = <24000000>;
> > > +};
> > > +
> > > +&emac {
> > > + nvmem-cells = <ð0_macaddress>;
> > > + nvmem-cell-names = "mac-address";
> > > + phy-handle = <&lan8720a>;
> > > + phy-mode = "rmii";
> > > + pinctrl-0 = <&rmii_pe_pins>;
> > > + pinctrl-names = "default";
> > > + status = "okay";
> > > +};
> > > +
> > > +/* Exposed as I2C on the card edge */
> > > +&i2c2 {
> > > + pinctrl-0 = <&i2c2_pins>;
> > > + pinctrl-names = "default";
> >
> > I wonder if this belongs here. In general we don't describe
> > pins/devices that are on generic connectors (like pin headers), because
> > the connection is determined by the user, not by the board.
> > In this case PD20 and PD21 could be used as generic GPIOs or as PWMs.
> > IIUC, even for the basic carrier those pins end up on headers, so even
> > there I wouldn't describe it. On the keypad carrier it's of course a
> > different story, since the MCP23008 is apparently soldered there.
>
> I get that part. However the module's description (as of yet unreleased)
> specifies those pins for this exact function as they are meant to be available
> on our modules using the same connector but other CPU/SoC. The Module's state
> that this is the default option but other function's can be reconfigured or
> they can be used as IO.
>
> If it's an issue I can remove those here, but I would still add them into the
> basic carrier as, even though they are only pin header, they are marked with
> the dedicated function of said pin. For example the headers there are
> specifically for "SPI", "I2S", "I2C" and the SD-Card slot.
For dedicated but otherwise unpopulated pins, we have in the past have
everything described as you already have, but with an explicit
status = "disabled";
along with a comment stating that it is normally unpopulated and up to the
end user to enable if they intend to use it. You can see examples of this
in the dts files of the Pine64.
I wouldn't say it's a preference, but it's been done for some development
boards.
ChenYu
> >
> > > +};
> > > +
> > > +/* Exposed as the QWIIC connector and used by the internal EEPROM */
> > > +&i2c3 {
> > > + pinctrl-0 = <&i2c3_pins>;
> > > + pinctrl-names = "default";
> > > + status = "okay";
> > > +
> > > + eeprom0: eeprom@50 {
> > > + compatible = "atmel,24c02"; /*
> actually it's a 24AA02E48 */
> > > + reg = <0x50>;
> > > + pagesize = <16>;
> > > + read-only;
> > > + vcc-supply = <®_vcc3v3>;
> > > +
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > +
> > > + eth0_macaddress: macaddress@fa {
> > > + reg = <0xfa 0x06>;
> > > + };
> > > + };
> > > +};
> > > +
> > > +/* Exposed as I2S on the card edge */
> > > +&i2s1 {
> > > + pinctrl-0 = <&i2s1_pins>, <&i2s1_din_pins>, <&i2s1_dout_pins>;
> > > + pinctrl-names = "default";
> >
> > Same story here, what prevents a user from using those edge pins as
> > GPIO or PWM?
> >
> > > +};
> > > +
> > > +/* Phy is on SoM. MDI signals pre-magentics are on the card edge */
> > > +&mdio {
> > > + lan8720a: ethernet-phy@0 {
> > > + compatible = "ethernet-phy-ieee802.3-c22";
> > > + reg = <0>;
> > > + };
> > > +};
> > > +
> > > +/* Exposed as SD on the card edge */
> > > +&mmc0 {
> > > + pinctrl-0 = <&mmc0_pins>;
> > > + pinctrl-names = "default";
> > > + vmmc-supply = <®_vcc3v3>;
> > > + broken-cd;
> > > + disable-wp;
> > > + bus-width = <4>;
> > > +};
> >
> > I think this node doesn't belong into the SoM .dtsi, as many details
> > are not set here, but on the carrier board: card detect, write protect,
> > Vmmc supply, and even bus width (could be 1 as well). So please move
> > this node to where the SD card connector sits. You might want to keep
> > the pinctrl nodes in here.
>
> Totally agree here, I will move this definition to the basic carrier, as it's
> currently the only one with the SD-Interface connected. However my question
> from above about the default function still applies here.
> >
> > > +
> > > +/* Connected to the on-board ESP32 */
> > > +&mmc1 {
> > > + pinctrl-0 = <&mmc1_pins>;
> > > + pinctrl-names = "default";
> > > + vmmc-supply = <®_vcc3v3>;
> > > + bus-width = <4>;
> > > + non-removable;
> > > + status = "okay";
> > > +};
> > > +
> > > +/* Connected to the on-board eMMC */
> > > +&mmc2 {
> > > + pinctrl-0 = <&mmc2_pins>;
> > > + pinctrl-names = "default";
> > > + vmmc-supply = <®_vcc3v3>;
> > > + vqmmc-supply = <®_vcc3v3>;
> > > + bus-width = <4>;
> > > + non-removable;
> > > + status = "okay";
> > > +};
> > > +
> > > +&pio {
> > > + vcc-pb-supply = <®_vcc3v3>;
> > > + vcc-pc-supply = <®_vcc3v3>;
> > > + vcc-pd-supply = <®_vcc3v3>;
> > > + vcc-pe-supply = <®_vcc3v3>;
> > > + vcc-pf-supply = <®_vcc3v3>;
> > > + vcc-pg-supply = <®_vcc3v3>;
> > > +
> > > + gpio-line-names = "", "", "", "", // PA
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "CAN0_TX",
> "CAN0_RX", // PB
> > > + "CAN1_TX",
> "CAN1_RX", "UART3_TX", "UART3_RX",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "eMMC_CLK",
> "eMMC_CMD", // PC
> > > + "eMMC_D2",
> "eMMC_D1", "eMMC_D0", "eMMC_D3",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "", //
> PD
> > > + "", "", "", "",
> > > + "", "", "SPI1_CS",
> "SPI1_CLK",
> > > + "SPI1_MOSI",
> "SPI1_MISO", "SPI1_HOLD", "SPI1_WP",
> > > + "PD16", "", "", "",
> > > + "I2C2_SCL",
> "I2C2_SDA", "PD22", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "ETH_CRSDV",
> "ETH_RXD0", "ETH_RXD1", "ETH_TXCK", // PE
> > > + "ETH_TXD0",
> "ETH_TXD1", "ETH_TXEN", "",
> > > + "ETH_MDC",
> "ETH_MDIO", "QWIIC_nINT", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "SD_D1", "SD_D0",
> "SD_CLK", "SD_CLK", // PF
> > > + "SD_D3", "SD_D2",
> "PF6", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "ESP_CLK",
> "ESP_CMD", "ESP_D0", "ESP_D1", // PG
> > > + "ESP_D2", "ESP_D3",
> "UART1_TXD", "UART1_RXD",
> > > + "ESP_nBOOT",
> "ESP_nRST", "I2C3_SCL", "I2C3_SDA",
> > > + "I2S1_WS",
> "I2S1_CLK", "I2S1_DIN0", "I2S1_DOUT0",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "",
> > > + "", "", "", "";
> > > +};
> > > +
> > > +/* Remove the unused CK pin from the pinctl as it is unconnected */
> > > +&rmii_pe_pins {
> > > + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
> > > + "PE5", "PE6", "PE8", "PE9";
> > > +};
> > > +
> > > +/* Exposed as SPI on the card-edge */
> > > +&spi1 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + pinctrl-0 = <&spi1_pins>;
> > > + pinctrl-names = "default";
> > > + cs-gpios = <0>;
> > > +};
> >
> > I wonder if this belongs here as well, since it's again just generic
> > edge pins.
>
> Same here too
> >
> > Cheers,
> > Andre
> >
> > > +
> > > +/* Connected to the Bootloader/Console of the ESP32 */
> > > +&uart1 {
> > > + pinctrl-0 = <&uart1_pg6_pins>;
> > > + pinctrl-names = "default";
> > > + status = "okay";
> > > +};
> > > +
> > > +/* Exposed as the Console/Debug UART on the card-edge */
> > > +&uart3 {
> > > + pinctrl-0 = <&uart3_pb_pins>;
> > > + pinctrl-names = "default";
> > > + status = "okay";
> > > +};
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 3/5] ARM: dts: sunxi: add support for NetCube Systems Nagami SoM
2025-07-08 15:19 ` Lukas Schmid
2025-07-08 15:35 ` Chen-Yu Tsai
@ 2025-07-08 16:39 ` Andrew Lunn
1 sibling, 0 replies; 12+ messages in thread
From: Andrew Lunn @ 2025-07-08 16:39 UTC (permalink / raw)
To: Lukas Schmid
Cc: Andre Przywara, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Maxime Ripard,
devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-riscv
On Tue, Jul 08, 2025 at 05:19:31PM +0200, Lukas Schmid wrote:
> On Dienstag, 8. Juli 2025 01:22:05 CEST Andre Przywara wrote:
> > On Mon, 7 Jul 2025 20:44:15 +0200
> > Lukas Schmid <lukas.schmid@netcube.li> wrote:
> >
> Hi Andre,
>
> > Hi Lukas,
> >
> > please try to refrain from sending subsequent patches too quickly, that
> > might just put off and confuse reviewers. To acknowledge a change
> > request, it is probably sufficient to just reply to the mail with a
> > confirmation.
>
> Sorry about that. I'm still trying to get the hang of this whole "submitting
> patches" thing. What is a good time/reason to send the next revision/version
> of a patchset?
It varies per subsystem. For netdev there is a clear rule to wait 24
hours. For other subsystems, it might not be documented. GregKH used
to say he would always respond within 2 weeks for USB patches. To some
extent, you just need to see how fast each Maintainer works, and
resubmit based on that.
Also, if there is a discussion going on, you need to wait for that
discussion to come to some sort of conclusion before reposting a new
version.
Andrew
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 4/5] ARM: dts: sunxi: add support for NetCube Systems Nagami Basic Carrier
2025-07-07 18:44 [PATCH v3 0/5] Add support for NetCube Systems Nagami SoM and its carrier boards Lukas Schmid
` (2 preceding siblings ...)
2025-07-07 18:44 ` [PATCH v3 3/5] ARM: dts: sunxi: add support for " Lukas Schmid
@ 2025-07-07 18:44 ` Lukas Schmid
2025-07-07 18:44 ` [PATCH v3 5/5] ARM: dts: sunxi: add support for NetCube Systems Nagami Keypad Carrier Lukas Schmid
4 siblings, 0 replies; 12+ messages in thread
From: Lukas Schmid @ 2025-07-07 18:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Maxime Ripard
Cc: Lukas Schmid, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-riscv
The NetCube Systems Nagami Basic Carrier is a Carrier for the Nagami SoM
It provides an ethernet port for the phy on the SoM and some USB-Ports.
All other interfaces and gpios are available on pinheader, except for the
SD-Interface which is available on a micro-sd slot.
Signed-off-by: Lukas Schmid <lukas.schmid@netcube.li>
---
arch/arm/boot/dts/allwinner/Makefile | 2 +
...n8i-t113s-netcube-nagami-basic-carrier.dts | 63 +++++++++++++++++++
2 files changed, 65 insertions(+)
create mode 100644 arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-basic-carrier.dts
diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile
index d799ad153..af287bb32 100644
--- a/arch/arm/boot/dts/allwinner/Makefile
+++ b/arch/arm/boot/dts/allwinner/Makefile
@@ -199,6 +199,7 @@ DTC_FLAGS_sun8i-h3-nanopi-r1 := -@
DTC_FLAGS_sun8i-h3-orangepi-pc := -@
DTC_FLAGS_sun8i-h3-bananapi-m2-plus-v1.2 := -@
DTC_FLAGS_sun8i-h3-orangepi-pc-plus := -@
+DTC_FLAGS_sun8i-t113s-netcube-nagami-basic-carrier := -@
DTC_FLAGS_sun8i-v3s-netcube-kumquat := -@
dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a23-evb.dtb \
@@ -257,6 +258,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-s3-lichee-zero-plus.dtb \
sun8i-s3-pinecube.dtb \
sun8i-t113s-mangopi-mq-r-t113.dtb \
+ sun8i-t113s-netcube-nagami-basic-carrier.dtb \
sun8i-t3-cqa3t-bv3.dtb \
sun8i-v3-sl631-imx179.dtb \
sun8i-v3s-anbernic-rg-nano.dtb \
diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-basic-carrier.dts b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-basic-carrier.dts
new file mode 100644
index 000000000..1c4e691cd
--- /dev/null
+++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-basic-carrier.dts
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2025 Lukas Schmid <lukas.schmid@netcube.li>
+ */
+
+/dts-v1/;
+#include "sun8i-t113s-netcube-nagami.dtsi"
+
+/ {
+ model = "NetCube Systems Nagami Basic Carrier Board";
+ compatible = "netcube,nagami-basic-carrier", "netcube,nagami",
+ "allwinner,sun8i-t113s";
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2s1 {
+ status = "okay";
+};
+
+&mmc0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ status = "okay";
+};
--
2.39.5
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v3 5/5] ARM: dts: sunxi: add support for NetCube Systems Nagami Keypad Carrier
2025-07-07 18:44 [PATCH v3 0/5] Add support for NetCube Systems Nagami SoM and its carrier boards Lukas Schmid
` (3 preceding siblings ...)
2025-07-07 18:44 ` [PATCH v3 4/5] ARM: dts: sunxi: add support for NetCube Systems Nagami Basic Carrier Lukas Schmid
@ 2025-07-07 18:44 ` Lukas Schmid
4 siblings, 0 replies; 12+ messages in thread
From: Lukas Schmid @ 2025-07-07 18:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Maxime Ripard
Cc: Lukas Schmid, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-riscv
The NetCube Systems Nagami Keypad Carrier uses the Nagami SoM and contains
a MCP23008 for connecting to a 4x3 matrix keypad and internal status led.
The I2C2 interface is connected to said MCP23008 and also a header for an
PN532 NFC-Module. It also provides a pin-header for a bi-color status led.
Ethernet with PoE support is available on a screwterminal after magnetics.
Signed-off-by: Lukas Schmid <lukas.schmid@netcube.li>
---
arch/arm/boot/dts/allwinner/Makefile | 1 +
...8i-t113s-netcube-nagami-keypad-carrier.dts | 164 ++++++++++++++++++
2 files changed, 165 insertions(+)
create mode 100644 arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-keypad-carrier.dts
diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile
index af287bb32..a2137bbe2 100644
--- a/arch/arm/boot/dts/allwinner/Makefile
+++ b/arch/arm/boot/dts/allwinner/Makefile
@@ -259,6 +259,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-s3-pinecube.dtb \
sun8i-t113s-mangopi-mq-r-t113.dtb \
sun8i-t113s-netcube-nagami-basic-carrier.dtb \
+ sun8i-t113s-netcube-nagami-keypad-carrier.dtb \
sun8i-t3-cqa3t-bv3.dtb \
sun8i-v3-sl631-imx179.dtb \
sun8i-v3s-anbernic-rg-nano.dtb \
diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-keypad-carrier.dts b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-keypad-carrier.dts
new file mode 100644
index 000000000..19608e12e
--- /dev/null
+++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-keypad-carrier.dts
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2025 Lukas Schmid <lukas.schmid@netcube.li>
+ */
+
+/dts-v1/;
+#include "sun8i-t113s-netcube-nagami.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "NetCube Systems Nagami Keypad Carrier Board";
+ compatible = "netcube,nagami-keypad-carrier", "netcube,nagami",
+ "allwinner,sun8i-t113s";
+
+ keypad: keypad {
+ compatible = "gpio-matrix-keypad";
+ debounce-delay-ms = <5>;
+ col-scan-delay-us = <2>;
+
+ row-gpios = <&mcp23008 0 0
+ &mcp23008 1 0
+ &mcp23008 2 0
+ &mcp23008 3 0>;
+
+ col-gpios = <&mcp23008 6 0
+ &mcp23008 5 0
+ &mcp23008 4 0>;
+
+ linux,keymap = <0x00000201
+ 0x00010202
+ 0x00020203
+ 0x01000204
+ 0x01010205
+ 0x01020206
+ 0x02000207
+ 0x02010208
+ 0x02020209
+ 0x0300020A
+ 0x03010200
+ 0x0302020D>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-heartbeat {
+ gpios = <&mcp23008 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_HEARTBEAT;
+ };
+
+ led_status_red: led-status-red {
+ gpios = <&pio 3 16 GPIO_ACTIVE_HIGH>; /* PD16 */
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ };
+
+ led_status_green: led-status-green {
+ gpios = <&pio 3 22 GPIO_ACTIVE_HIGH>; /* PD22 */
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ };
+ };
+
+ multi-led {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_MULTI>;
+ function = LED_FUNCTION_STATUS;
+ leds = <&led_status_red &led_status_green>;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+
+ mcp23008: gpio@20 {
+ compatible = "microchip,mcp23008";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+ interrupts-extended = <&pio 5 6 IRQ_TYPE_LEVEL_LOW>; /* PF6 */
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&pio {
+ gpio-line-names = "", "", "", "", // PA
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "", // PB
+ "", "", "UART3_TX", "UART3_RX",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "eMMC_CLK", "eMMC_CMD", // PC
+ "eMMC_D2", "eMMC_D1", "eMMC_D0", "eMMC_D3",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "", // PD
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "LED_STATUS_RED", "", "", "",
+ "I2C2_SCL", "I2C2_SDA", "LED_STATUS_GREEN", "",
+ "", "", "", "",
+ "", "", "", "",
+ "ETH_CRSDV", "ETH_RXD0", "ETH_RXD1", "ETH_TXCK", // PE
+ "ETH_TXD0", "ETH_TXD1", "ETH_TXEN", "",
+ "ETH_MDC", "ETH_MDIO", "QWIIC_nINT", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "", // PF
+ "", "", "KEY_nINT", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "ESP_CLK", "ESP_CMD", "ESP_D0", "ESP_D1", // PG
+ "ESP_D2", "ESP_D3", "UART1_TXD", "UART1_RXD",
+ "ESP_nBOOT", "ESP_nRST", "I2C3_SCL", "I2C3_SDA",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
--
2.39.5
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