From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F40D6C83F1B for ; Mon, 14 Jul 2025 07:38:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Cc:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=glYySSu5bOt/NAhJDzz3/8dWdR+IuTirRor33nYnHck=; b=clcxxufuMczbIH EbMhVyO09UsEl6oVYscgqEsCpjp57NTybtWcRYm7rZ8NMQJIoH2ptHoaRnV4D6/A2798nF4rtmprw 4638AoMpd5MGHw1/vZvkbniRZArZ5cg8MPw+XFWB/mUut38fENBbE6Bf1sULlZFVCL9DQWZR1PoCt hWV6KjtZn70bHVeWDu3Q/iePEQJAsc/urweRgC35RAiF0T6ZpKUK63dXhSCmUYorJKVXnMvjLzwqO GH052cH5ZzTThivkv8WLbh2sk9sM2skfCy6wFe9MUG8hHK5v7kPbeHW0K1w9schhA8NHFezqrN3JO DXw6y88IGn3M4GDW6HeA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1ubDlk-00000001UqZ-0gYR; Mon, 14 Jul 2025 07:38:36 +0000 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1ubDRs-00000001Rx3-2N5r for linux-arm-kernel@lists.infradead.org; Mon, 14 Jul 2025 07:18:06 +0000 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 14 Jul 2025 15:17:53 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 14 Jul 2025 15:17:53 +0800 From: Ryan Chen To: ryan_chen , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Kevin Chen , , , , Subject: [PATCH] dt-bindings: interrupt-controller: aspeed: Refine AST2700 binding description and example Date: Mon, 14 Jul 2025 15:17:53 +0800 Message-ID: <20250714071753.2653620-1-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250714_001804_795392_B2082357 X-CRM114-Status: GOOD ( 13.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org - Update block diagram for better readability and accuracy. - Clarify the relationship and function of INTC0, INTC1, and the GIC. - Documentation and example refine. This enhances the documentation quality and helps developers understand the interrupt controller hierarchy and usage. Signed-off-by: Ryan Chen --- .../aspeed,ast2700-intc.yaml | 155 +++++++++++++----- 1 file changed, 112 insertions(+), 43 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml index 55636d06a674..751a07d49c90 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml @@ -10,6 +10,33 @@ description: This interrupt controller hardware is second level interrupt controller that is hooked to a parent interrupt controller. It's useful to combine multiple interrupt sources into 1 interrupt to parent interrupt controller. + Depend to which INTC0 or INTC1 used. + INTC0 and INTC1 are two kinds of interrupt controller with enable and raw + status registers for use. + INTC0 is used to assert GIC if interrupt in INTC1 asserted. + INTC1 is used to assert INTC0 if interrupt of modules asserted. + +-----+ +---------+ + | GIC |---| INTC0 | + +-----+ +---------+ + +---------+ + | |---module0 + | INTC0_0 |---module1 + | |---... + +---------+---module31 + |---.... | + +---------+ + | | +---------+ + | INTC0_11| +---| INTC1 | + | | +---------+ + +---------+ +---------+---module0 + | INTC1_0 |---module1 + | |---... + +---------+---module31 + ... + +---------+---module0 + | INTC1_5 |---module1 + | |---... + +---------+---module31 maintainers: - Kevin Chen @@ -17,49 +44,67 @@ maintainers: properties: compatible: enum: - - aspeed,ast2700-intc-ic + - aspeed,ast2700-intc0 + - aspeed,ast2700-intc1 reg: maxItems: 1 - interrupt-controller: true + 'address-cells': + const: 2 - '#interrupt-cells': + 'size-cells': const: 2 - description: - The first cell is the IRQ number, the second cell is the trigger - type as defined in interrupt.txt in this directory. - - interrupts: - maxItems: 6 - description: | - Depend to which INTC0 or INTC1 used. - INTC0 and INTC1 are two kinds of interrupt controller with enable and raw - status registers for use. - INTC0 is used to assert GIC if interrupt in INTC1 asserted. - INTC1 is used to assert INTC0 if interrupt of modules asserted. - +-----+ +-------+ +---------+---module0 - | GIC |---| INTC0 |--+--| INTC1_0 |---module2 - | | | | | | |---... - +-----+ +-------+ | +---------+---module31 - | - | +---------+---module0 - +---| INTC1_1 |---module2 - | | |---... - | +---------+---module31 - ... - | +---------+---module0 - +---| INTC1_5 |---module2 - | |---... - +---------+---module31 + ranges: true + +patternProperties: + "^interrupt-controller@": + type: object + description: Interrupt group child nodes + additionalProperties: false + + properties: + compatible: + enum: + - aspeed,ast2700-intc-ic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: | + The first cell is the IRQ number, the second cell is the trigger + type as defined in interrupt.txt in this directory. + + interrupts: + minItems: 1 + maxItems: 6 + description: | + The interrupts provided by this interrupt controller. + + interrupts-extended: + minItems: 1 + maxItems: 6 + description: | + This property is required when defining a cascaded interrupt controller + that is connected under another interrupt controller. It specifies the + parent interrupt(s) in the upstream controller to which this controller + is connected. + + required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts required: - compatible - reg - - interrupt-controller - - '#interrupt-cells' - - interrupts additionalProperties: false @@ -68,19 +113,43 @@ examples: #include bus { + #address-cells = <2>; + #size-cells = <2>; + + intc0: interrupt-controller@12100000 { + compatible = "aspeed,ast2700-intc0"; + reg = <0 0x12100000 0 0x4000>; + ranges = <0x0 0x0 0x0 0x12100000 0x0 0x4000>; + #address-cells = <2>; + #size-cells = <2>; + + intc0_11: interrupt-controller@1b00 { + compatible = "aspeed,ast2700-intc-ic"; + reg = <0 0x12101b00 0x10>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = , + , + , + , + , + ; + }; + }; + + intc1: interrupt-controller@14c18000 { + compatible = "aspeed,ast2700-intc1"; + reg = <0 0x14c18000 0 0x400>; + ranges = <0x0 0x0 0x0 0x14c18000 0x0 0x400>; #address-cells = <2>; #size-cells = <2>; - interrupt-controller@12101b00 { - compatible = "aspeed,ast2700-intc-ic"; - reg = <0 0x12101b00 0 0x10>; - #interrupt-cells = <2>; - interrupt-controller; - interrupts = , - , - , - , - , - ; + intc1_0: interrupt-controller@100 { + compatible = "aspeed,ast2700-intc-ic"; + reg = <0x0 0x100 0x0 0x10>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&intc0_11 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + }; }; -- 2.34.1