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Mon, 14 Jul 2025 05:38:11 -0700 (PDT) Received: from playground.localdomain ([92.120.5.7]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e829402asm805005266b.121.2025.07.14.05.38.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jul 2025 05:38:10 -0700 (PDT) From: Laurentiu Mihalcea To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Shawn Guo , Sascha Hauer , Fabio Estevam Cc: Pengutronix Kernel Team , linux-pwm@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] pwm: imx-tpm: reset counter if CMOD is 0 Date: Mon, 14 Jul 2025 08:36:34 -0400 Message-Id: <20250714123634.6442-1-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250714_053813_528474_A8FE832B X-CRM114-Status: GOOD ( 14.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Laurentiu Mihalcea As per the i.MX93 TRM, section 67.3.2.1 "MOD register update", the value of the TPM counter does NOT get updated when writing MOD.MOD unless SC.CMOD != 0. Therefore, with the current code, assuming the following sequence: 1) pwm_disable() 2) pwm_apply_might_sleep() /* period is changed here */ 3) pwm_enable() and assuming only one channel is active, if CNT.COUNT is higher than the MOD.MOD value written during the pwm_apply_might_sleep() call then, when re-enabling the PWM during pwm_enable(), the counter will end up resetting after UINT32_MAX - CNT.COUNT + MOD.MOD cycles instead of MOD.MOD cycles as normally expected. Fix this problem by forcing a reset of the TPM counter before MOD.MOD is written. Signed-off-by: Laurentiu Mihalcea --- Changes in v2: - dropped the "VERY IMPORTANT" bit as per Uwe's suggestion. - Link to v1: https://lore.kernel.org/lkml/20250701220147.1007786-1-laurentiumihalcea111@gmail.com/ drivers/pwm/pwm-imx-tpm.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pwm/pwm-imx-tpm.c b/drivers/pwm/pwm-imx-tpm.c index 7ee7b65b9b90..b15c22796ba9 100644 --- a/drivers/pwm/pwm-imx-tpm.c +++ b/drivers/pwm/pwm-imx-tpm.c @@ -204,6 +204,19 @@ static int pwm_imx_tpm_apply_hw(struct pwm_chip *chip, val |= FIELD_PREP(PWM_IMX_TPM_SC_PS, p->prescale); writel(val, tpm->base + PWM_IMX_TPM_SC); + /* + * if CMOD is set to 0 then writing MOD will NOT reset the + * value of the TPM counter. + * + * Therefore, if CNT.COUNT > MOD.MOD, the counter will reset + * after UINT32_MAX - CNT.COUNT + MOD.MOD cycles, which is + * incorrect. + * + * To avoid this, we need to force a reset of the + * counter before writing the new MOD value. + */ + if (!cmod) + writel(0x0, tpm->base + PWM_IMX_TPM_CNT); /* * set period count: * if the PWM is disabled (CMOD[1:0] = 2b00), then MOD register -- 2.34.1