* [PATCH 0/2] clk: amlogic: add video-related clocks for S4 SoC
@ 2025-07-15 12:51 Chuan Liu via B4 Relay
2025-07-15 12:51 ` [PATCH 1/2] dt-bindings: clock: add video clock indices for Amlogic " Chuan Liu via B4 Relay
2025-07-15 12:51 ` [PATCH 2/2] clk: amlogic: add video-related clocks for " Chuan Liu via B4 Relay
0 siblings, 2 replies; 5+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-07-15 12:51 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-clk, devicetree, linux-kernel, linux-amlogic,
linux-arm-kernel, Chuan Liu
This patch introduces new clock support for video processing components
including the encoder, demodulator and CVBS interface modules.
The related clocks have passed clk-measure verification.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
Chuan Liu (2):
dt-bindings: clock: add video clock indices for Amlogic S4 SoC
clk: amlogic: add video-related clocks for S4 SoC
drivers/clk/meson/s4-peripherals.c | 256 +++++++++++++++++++++
.../clock/amlogic,s4-peripherals-clkc.h | 14 ++
2 files changed, 270 insertions(+)
---
base-commit: 8a65268500b00ecee5402ef9f80618ff73f30707
change-id: 20250715-add_video_clk-dc38b5459018
Best regards,
--
Chuan Liu <chuan.liu@amlogic.com>
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 1/2] dt-bindings: clock: add video clock indices for Amlogic S4 SoC 2025-07-15 12:51 [PATCH 0/2] clk: amlogic: add video-related clocks for S4 SoC Chuan Liu via B4 Relay @ 2025-07-15 12:51 ` Chuan Liu via B4 Relay 2025-07-20 22:31 ` Rob Herring (Arm) 2025-07-15 12:51 ` [PATCH 2/2] clk: amlogic: add video-related clocks for " Chuan Liu via B4 Relay 1 sibling, 1 reply; 5+ messages in thread From: Chuan Liu via B4 Relay @ 2025-07-15 12:51 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman, Martin Blumenstingl Cc: linux-clk, devicetree, linux-kernel, linux-amlogic, linux-arm-kernel, Chuan Liu From: Chuan Liu <chuan.liu@amlogic.com> Add indices for video encoder, demodulator and CVBS clocks. Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> --- include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h index 861a331963ac..a1cd22b25102 100644 --- a/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h +++ b/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h @@ -232,5 +232,19 @@ #define CLKID_HDCP22_SKPCLK_SEL 222 #define CLKID_HDCP22_SKPCLK_DIV 223 #define CLKID_HDCP22_SKPCLK 224 +#define CLKID_CTS_ENCL_SEL 225 +#define CLKID_CTS_ENCL 226 +#define CLKID_LCD_AN_SEL 227 +#define CLKID_LCD_AN_PH2 228 +#define CLKID_LCD_AN_PH3 229 +#define CLKID_CDAC_SEL 230 +#define CLKID_CDAC_DIV 231 +#define CLKID_CDAC 232 +#define CLKID_DEMOD_CORE_SEL 233 +#define CLKID_DEMOD_CORE_DIV 234 +#define CLKID_DEMOD_CORE 235 +#define CLKID_ADC_EXTCLK_IN_SEL 236 +#define CLKID_ADC_EXTCLK_IN_DIV 237 +#define CLKID_ADC_EXTCLK_IN 238 #endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H */ -- 2.42.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clock: add video clock indices for Amlogic S4 SoC 2025-07-15 12:51 ` [PATCH 1/2] dt-bindings: clock: add video clock indices for Amlogic " Chuan Liu via B4 Relay @ 2025-07-20 22:31 ` Rob Herring (Arm) 0 siblings, 0 replies; 5+ messages in thread From: Rob Herring (Arm) @ 2025-07-20 22:31 UTC (permalink / raw) To: Chuan Liu Cc: linux-clk, Michael Turquette, linux-kernel, Neil Armstrong, Jerome Brunet, Conor Dooley, Stephen Boyd, Krzysztof Kozlowski, Martin Blumenstingl, devicetree, linux-arm-kernel, linux-amlogic, Kevin Hilman On Tue, 15 Jul 2025 20:51:38 +0800, Chuan Liu wrote: > Add indices for video encoder, demodulator and CVBS clocks. > > Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> > --- > include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > Acked-by: Rob Herring (Arm) <robh@kernel.org> ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] clk: amlogic: add video-related clocks for S4 SoC 2025-07-15 12:51 [PATCH 0/2] clk: amlogic: add video-related clocks for S4 SoC Chuan Liu via B4 Relay 2025-07-15 12:51 ` [PATCH 1/2] dt-bindings: clock: add video clock indices for Amlogic " Chuan Liu via B4 Relay @ 2025-07-15 12:51 ` Chuan Liu via B4 Relay 2025-07-15 13:08 ` Chuan Liu 1 sibling, 1 reply; 5+ messages in thread From: Chuan Liu via B4 Relay @ 2025-07-15 12:51 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman, Martin Blumenstingl Cc: linux-clk, devicetree, linux-kernel, linux-amlogic, linux-arm-kernel, Chuan Liu From: Chuan Liu <chuan.liu@amlogic.com> Add video encoder, demodulator and CVBS clocks. Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> --- drivers/clk/meson/s4-peripherals.c | 256 +++++++++++++++++++++++++++++++++++++ 1 file changed, 256 insertions(+) diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peripherals.c index c9400cf54c84..f43526d506b1 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -44,6 +44,7 @@ #define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8 #define CLKCTRL_VAPBCLK_CTRL 0x0fc #define CLKCTRL_HDCP22_CTRL 0x100 +#define CLKCTRL_CDAC_CLK_CTRL 0x108 #define CLKCTRL_VDEC_CLK_CTRL 0x140 #define CLKCTRL_VDEC2_CLK_CTRL 0x144 #define CLKCTRL_VDEC3_CLK_CTRL 0x148 @@ -1117,6 +1118,22 @@ static struct clk_regmap s4_cts_encp_sel = { }, }; +static struct clk_regmap s4_cts_encl_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_VIID_CLK_DIV, + .mask = 0xf, + .shift = 12, + .table = mux_table_cts_sel, + }, + .hw.init = &(struct clk_init_data){ + .name = "cts_encl_sel", + .ops = &clk_regmap_mux_ops, + .parent_hws = s4_cts_parent_hws, + .num_parents = ARRAY_SIZE(s4_cts_parent_hws), + .flags = CLK_SET_RATE_PARENT, + }, +}; + static struct clk_regmap s4_cts_vdac_sel = { .data = &(struct clk_regmap_mux_data){ .offset = CLKCTRL_VIID_CLK_DIV, @@ -1196,6 +1213,22 @@ static struct clk_regmap s4_cts_encp = { }, }; +static struct clk_regmap s4_cts_encl = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_VID_CLK_CTRL2, + .bit_idx = 3, + }, + .hw.init = &(struct clk_init_data) { + .name = "cts_encl", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &s4_cts_encl_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + static struct clk_regmap s4_cts_vdac = { .data = &(struct clk_regmap_gate_data){ .offset = CLKCTRL_VID_CLK_CTRL2, @@ -1228,6 +1261,56 @@ static struct clk_regmap s4_hdmi_tx = { }, }; +static struct clk_regmap s4_lcd_an_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_VIID_CLK_DIV, + .mask = 0x1, + .shift = 11, + }, + .hw.init = &(struct clk_init_data){ + .name = "lcd_an_sel", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &s4_vclk_div6.hw, + &s4_vclk_div12.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_lcd_an_ph2 = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_VID_CLK_CTRL2, + .bit_idx = 7, + }, + .hw.init = &(struct clk_init_data) { + .name = "lcd_an_ph2", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &s4_lcd_an_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_lcd_an_ph3 = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_VID_CLK_CTRL2, + .bit_idx = 7, + }, + .hw.init = &(struct clk_init_data) { + .name = "lcd_an_ph3", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &s4_lcd_an_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + /* HDMI Clocks */ static const struct clk_parent_data s4_hdmi_parent_data[] = { { .fw_name = "xtal", }, @@ -3174,6 +3257,165 @@ static struct clk_regmap s4_gen_clk = { }, }; +/* CVBS DAC */ +static struct clk_regmap s4_cdac_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_CDAC_CLK_CTRL, + .mask = 0x3, + .shift = 16, + }, + .hw.init = &(struct clk_init_data){ + .name = "cdac_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .fw_name = "xtal", }, + { .fw_name = "fclk_div5" }, + }, + .num_parents = 2, + }, +}; + +static struct clk_regmap s4_cdac_div = { + .data = &(struct clk_regmap_div_data) { + .offset = CLKCTRL_CDAC_CLK_CTRL, + .shift = 0, + .width = 16, + }, + .hw.init = &(struct clk_init_data){ + .name = "cdac_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &s4_cdac_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_cdac = { + .data = &(struct clk_regmap_gate_data) { + .offset = CLKCTRL_CDAC_CLK_CTRL, + .bit_idx = 20, + }, + .hw.init = &(struct clk_init_data){ + .name = "cdac", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &s4_cdac_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_demod_core_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_DEMOD_CLK_CTRL, + .mask = 0x3, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "demod_core_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .fw_name = "xtal" }, + { .fw_name = "fclk_div7" }, + { .fw_name = "fclk_div4" } + }, + .num_parents = 3, + }, +}; + +static struct clk_regmap s4_demod_core_div = { + .data = &(struct clk_regmap_div_data) { + .offset = CLKCTRL_DEMOD_CLK_CTRL, + .shift = 0, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "demod_core_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &s4_demod_core_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_demod_core = { + .data = &(struct clk_regmap_gate_data) { + .offset = CLKCTRL_DEMOD_CLK_CTRL, + .bit_idx = 8 + }, + .hw.init = &(struct clk_init_data){ + .name = "demod_core", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &s4_demod_core_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/* CVBS ADC */ +static struct clk_regmap s4_adc_extclk_in_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_DEMOD_CLK_CTRL, + .mask = 0x7, + .shift = 25, + }, + .hw.init = &(struct clk_init_data){ + .name = "adc_extclk_in_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .fw_name = "xtal" }, + { .fw_name = "fclk_div4" }, + { .fw_name = "fclk_div3" }, + { .fw_name = "fclk_div5" }, + { .fw_name = "fclk_div7" }, + { .fw_name = "mpll2" }, + { .fw_name = "gp0_pll" }, + { .fw_name = "hifi_pll" } + }, + .num_parents = 8, + }, +}; + +static struct clk_regmap s4_adc_extclk_in_div = { + .data = &(struct clk_regmap_div_data) { + .offset = CLKCTRL_DEMOD_CLK_CTRL, + .shift = 16, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "adc_extclk_in_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &s4_adc_extclk_in_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_adc_extclk_in = { + .data = &(struct clk_regmap_gate_data) { + .offset = CLKCTRL_DEMOD_CLK_CTRL, + .bit_idx = 24 + }, + .hw.init = &(struct clk_init_data){ + .name = "adc_extclk_in", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &s4_adc_extclk_in_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + #define MESON_GATE(_name, _reg, _bit) \ MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw) @@ -3453,6 +3695,20 @@ static struct clk_hw *s4_periphs_hw_clks[] = { [CLKID_HDCP22_SKPCLK_SEL] = &s4_hdcp22_skpclk_mux.hw, [CLKID_HDCP22_SKPCLK_DIV] = &s4_hdcp22_skpclk_div.hw, [CLKID_HDCP22_SKPCLK] = &s4_hdcp22_skpclk_gate.hw, + [CLKID_CTS_ENCL_SEL] = &s4_cts_encl_sel.hw, + [CLKID_CTS_ENCL] = &s4_cts_encl.hw, + [CLKID_LCD_AN_SEL] = &s4_lcd_an_sel.hw, + [CLKID_LCD_AN_PH2] = &s4_lcd_an_ph2.hw, + [CLKID_LCD_AN_PH3] = &s4_lcd_an_ph3.hw, + [CLKID_CDAC_SEL] = &s4_cdac_sel.hw, + [CLKID_CDAC_DIV] = &s4_cdac_div.hw, + [CLKID_CDAC] = &s4_cdac.hw, + [CLKID_DEMOD_CORE_SEL] = &s4_demod_core_sel.hw, + [CLKID_DEMOD_CORE_DIV] = &s4_demod_core_div.hw, + [CLKID_DEMOD_CORE] = &s4_demod_core.hw, + [CLKID_ADC_EXTCLK_IN_SEL] = &s4_adc_extclk_in_sel.hw, + [CLKID_ADC_EXTCLK_IN_DIV] = &s4_adc_extclk_in_div.hw, + [CLKID_ADC_EXTCLK_IN] = &s4_adc_extclk_in.hw, }; static const struct regmap_config clkc_regmap_config = { -- 2.42.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] clk: amlogic: add video-related clocks for S4 SoC 2025-07-15 12:51 ` [PATCH 2/2] clk: amlogic: add video-related clocks for " Chuan Liu via B4 Relay @ 2025-07-15 13:08 ` Chuan Liu 0 siblings, 0 replies; 5+ messages in thread From: Chuan Liu @ 2025-07-15 13:08 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman, Martin Blumenstingl Cc: linux-clk, devicetree, linux-kernel, linux-amlogic, linux-arm-kernel On 7/15/2025 8:51 PM, Chuan Liu via B4 Relay wrote: > [ EXTERNAL EMAIL ] > > From: Chuan Liu <chuan.liu@amlogic.com> > > Add video encoder, demodulator and CVBS clocks. > > Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> > --- > drivers/clk/meson/s4-peripherals.c | 256 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 256 insertions(+) > > diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peripherals.c > index c9400cf54c84..f43526d506b1 100644 > --- a/drivers/clk/meson/s4-peripherals.c > +++ b/drivers/clk/meson/s4-peripherals.c > @@ -44,6 +44,7 @@ > #define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8 > #define CLKCTRL_VAPBCLK_CTRL 0x0fc > #define CLKCTRL_HDCP22_CTRL 0x100 > +#define CLKCTRL_CDAC_CLK_CTRL 0x108 > #define CLKCTRL_VDEC_CLK_CTRL 0x140 > #define CLKCTRL_VDEC2_CLK_CTRL 0x144 > #define CLKCTRL_VDEC3_CLK_CTRL 0x148 > @@ -1117,6 +1118,22 @@ static struct clk_regmap s4_cts_encp_sel = { > }, > }; > > +static struct clk_regmap s4_cts_encl_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_VIID_CLK_DIV, > + .mask = 0xf, > + .shift = 12, > + .table = mux_table_cts_sel, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "cts_encl_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = s4_cts_parent_hws, > + .num_parents = ARRAY_SIZE(s4_cts_parent_hws), > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > static struct clk_regmap s4_cts_vdac_sel = { > .data = &(struct clk_regmap_mux_data){ > .offset = CLKCTRL_VIID_CLK_DIV, > @@ -1196,6 +1213,22 @@ static struct clk_regmap s4_cts_encp = { > }, > }; > > +static struct clk_regmap s4_cts_encl = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_VID_CLK_CTRL2, > + .bit_idx = 3, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "cts_encl", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &s4_cts_encl_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > static struct clk_regmap s4_cts_vdac = { > .data = &(struct clk_regmap_gate_data){ > .offset = CLKCTRL_VID_CLK_CTRL2, > @@ -1228,6 +1261,56 @@ static struct clk_regmap s4_hdmi_tx = { > }, > }; > > +static struct clk_regmap s4_lcd_an_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_VIID_CLK_DIV, > + .mask = 0x1, > + .shift = 11, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "lcd_an_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &s4_vclk_div6.hw, > + &s4_vclk_div12.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap s4_lcd_an_ph2 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_VID_CLK_CTRL2, > + .bit_idx = 7, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "lcd_an_ph2", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &s4_lcd_an_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap s4_lcd_an_ph3 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_VID_CLK_CTRL2, > + .bit_idx = 7, Apologies for the oversight - this should be '.bit_idx = 6'. I'll correct it in the next revision. > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "lcd_an_ph3", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &s4_lcd_an_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > /* HDMI Clocks */ > static const struct clk_parent_data s4_hdmi_parent_data[] = { > { .fw_name = "xtal", }, > @@ -3174,6 +3257,165 @@ static struct clk_regmap s4_gen_clk = { > }, > }; > > +/* CVBS DAC */ > +static struct clk_regmap s4_cdac_sel = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_CDAC_CLK_CTRL, > + .mask = 0x3, > + .shift = 16, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "cdac_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .fw_name = "xtal", }, > + { .fw_name = "fclk_div5" }, > + }, > + .num_parents = 2, > + }, > +}; > + > +static struct clk_regmap s4_cdac_div = { > + .data = &(struct clk_regmap_div_data) { > + .offset = CLKCTRL_CDAC_CLK_CTRL, > + .shift = 0, > + .width = 16, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "cdac_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &s4_cdac_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap s4_cdac = { > + .data = &(struct clk_regmap_gate_data) { > + .offset = CLKCTRL_CDAC_CLK_CTRL, > + .bit_idx = 20, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "cdac", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &s4_cdac_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap s4_demod_core_sel = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_DEMOD_CLK_CTRL, > + .mask = 0x3, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "demod_core_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .fw_name = "xtal" }, > + { .fw_name = "fclk_div7" }, > + { .fw_name = "fclk_div4" } > + }, > + .num_parents = 3, > + }, > +}; > + > +static struct clk_regmap s4_demod_core_div = { > + .data = &(struct clk_regmap_div_data) { > + .offset = CLKCTRL_DEMOD_CLK_CTRL, > + .shift = 0, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "demod_core_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &s4_demod_core_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap s4_demod_core = { > + .data = &(struct clk_regmap_gate_data) { > + .offset = CLKCTRL_DEMOD_CLK_CTRL, > + .bit_idx = 8 > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "demod_core", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &s4_demod_core_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +/* CVBS ADC */ > +static struct clk_regmap s4_adc_extclk_in_sel = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_DEMOD_CLK_CTRL, > + .mask = 0x7, > + .shift = 25, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "adc_extclk_in_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .fw_name = "xtal" }, > + { .fw_name = "fclk_div4" }, > + { .fw_name = "fclk_div3" }, > + { .fw_name = "fclk_div5" }, > + { .fw_name = "fclk_div7" }, > + { .fw_name = "mpll2" }, > + { .fw_name = "gp0_pll" }, > + { .fw_name = "hifi_pll" } > + }, > + .num_parents = 8, > + }, > +}; > + > +static struct clk_regmap s4_adc_extclk_in_div = { > + .data = &(struct clk_regmap_div_data) { > + .offset = CLKCTRL_DEMOD_CLK_CTRL, > + .shift = 16, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "adc_extclk_in_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &s4_adc_extclk_in_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap s4_adc_extclk_in = { > + .data = &(struct clk_regmap_gate_data) { > + .offset = CLKCTRL_DEMOD_CLK_CTRL, > + .bit_idx = 24 > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "adc_extclk_in", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &s4_adc_extclk_in_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > #define MESON_GATE(_name, _reg, _bit) \ > MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw) > > @@ -3453,6 +3695,20 @@ static struct clk_hw *s4_periphs_hw_clks[] = { > [CLKID_HDCP22_SKPCLK_SEL] = &s4_hdcp22_skpclk_mux.hw, > [CLKID_HDCP22_SKPCLK_DIV] = &s4_hdcp22_skpclk_div.hw, > [CLKID_HDCP22_SKPCLK] = &s4_hdcp22_skpclk_gate.hw, > + [CLKID_CTS_ENCL_SEL] = &s4_cts_encl_sel.hw, > + [CLKID_CTS_ENCL] = &s4_cts_encl.hw, > + [CLKID_LCD_AN_SEL] = &s4_lcd_an_sel.hw, > + [CLKID_LCD_AN_PH2] = &s4_lcd_an_ph2.hw, > + [CLKID_LCD_AN_PH3] = &s4_lcd_an_ph3.hw, > + [CLKID_CDAC_SEL] = &s4_cdac_sel.hw, > + [CLKID_CDAC_DIV] = &s4_cdac_div.hw, > + [CLKID_CDAC] = &s4_cdac.hw, > + [CLKID_DEMOD_CORE_SEL] = &s4_demod_core_sel.hw, > + [CLKID_DEMOD_CORE_DIV] = &s4_demod_core_div.hw, > + [CLKID_DEMOD_CORE] = &s4_demod_core.hw, > + [CLKID_ADC_EXTCLK_IN_SEL] = &s4_adc_extclk_in_sel.hw, > + [CLKID_ADC_EXTCLK_IN_DIV] = &s4_adc_extclk_in_div.hw, > + [CLKID_ADC_EXTCLK_IN] = &s4_adc_extclk_in.hw, > }; > > static const struct regmap_config clkc_regmap_config = { > > -- > 2.42.0 > > ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-07-20 22:34 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-07-15 12:51 [PATCH 0/2] clk: amlogic: add video-related clocks for S4 SoC Chuan Liu via B4 Relay 2025-07-15 12:51 ` [PATCH 1/2] dt-bindings: clock: add video clock indices for Amlogic " Chuan Liu via B4 Relay 2025-07-20 22:31 ` Rob Herring (Arm) 2025-07-15 12:51 ` [PATCH 2/2] clk: amlogic: add video-related clocks for " Chuan Liu via B4 Relay 2025-07-15 13:08 ` Chuan Liu
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