From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3A49C83F1D for ; Tue, 15 Jul 2025 04:06:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=oQh6vV240tnImvumdSacIM1S/td0hkqCP9jGtPpAdBo=; b=X6dYqzxGr/aPTO/+k4OorsbUCD OSti3UEVbmxY69dWxVXGK1/tov0J89T6XSgsKrWN1QXegUZ8obBThWz4onW4967WvNayhKM2DNwHo AzL2KGjbuBESHZUEnESE+ikL6m5kX9ittcYQ0yz8RXRomzoCcS1hI+kgBkQNuAubHi+i/YvOI+yu9 LKZI8UdWz69sSND2C03WcIXZi5J4oT5vwG6WU6ERnSh4bQbMInPlK0swoEcm+JW8mJXq/dDjr/h+u E4uyNDqdLPfroQLPdBq0pnh9v4RhNVl2t501iEG/1h8zWZGAB9jjdp5mImar/8VXzVit+v2hm8d/3 jOwyjmcQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1ubWvb-00000003yEF-1VyD; Tue, 15 Jul 2025 04:06:03 +0000 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1ubWZr-00000003vKr-3yp1 for linux-arm-kernel@lists.infradead.org; Tue, 15 Jul 2025 03:43:37 +0000 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 15 Jul 2025 11:43:20 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 15 Jul 2025 11:43:20 +0800 From: Jacky Chou To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 01/10] dt-bindings: soc: aspeed: Add ASPEED PCIe Config support Date: Tue, 15 Jul 2025 11:43:11 +0800 Message-ID: <20250715034320.2553837-2-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> References: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250714_204335_990006_95313B9F X-CRM114-Status: GOOD ( 11.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the ASPEED PCIe configuration syscon block. This shared register space is used by multiple PCIe-related devices to coordinate and manage common PCIe settings. The binding describes the required compatible strings and register space for the configuration node. Signed-off-by: Jacky Chou --- .../bindings/soc/aspeed/aspeed,pcie-cfg.yaml | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/aspeed/aspeed,pcie-cfg.yaml diff --git a/Documentation/devicetree/bindings/soc/aspeed/aspeed,pcie-cfg.yaml b/Documentation/devicetree/bindings/soc/aspeed/aspeed,pcie-cfg.yaml new file mode 100644 index 000000000000..6b282f06b914 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/aspeed/aspeed,pcie-cfg.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/aspeed/aspeed,pcie-cfg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED PCIe Configuration + +maintainers: + - Jacky Chou + +description: | + The ASPEED PCIe configuration syscon block provides a set of registers shared + by multiple PCIe-related devices within the SoC. This node represents the + common configuration space that allows these devices to coordinate and manage + shared PCIe settings, including address mapping, control, and status + registers. The syscon interface enables for various PCIe devices to access + and modify these shared registers in a consistent and centralized manner. + +properties: + compatible: + items: + - enum: + - aspeed,pcie-cfg + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@1e770000 { + compatible = "aspeed,pcie-cfg", "syscon"; + reg = <0x1e770000 0x80>; + }; -- 2.43.0