From: Jacky Chou <jacky_chou@aspeedtech.com>
To: <bhelgaas@google.com>, <lpieralisi@kernel.org>,
<kwilczynski@kernel.org>, <mani@kernel.org>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>, <joel@jms.id.au>,
<andrew@codeconstruct.com.au>, <linux-aspeed@lists.ozlabs.org>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Cc: <openbmc@lists.ozlabs.org>, <linux-gpio@vger.kernel.org>,
<linus.walleij@linaro.org>, <p.zabel@pengutronix.de>,
<BMC-SW@aspeedtech.com>
Subject: [PATCH v2 02/10] dt-bindings: soc: aspeed: Add ASPEED PCIe PHY support
Date: Tue, 15 Jul 2025 11:43:12 +0800 [thread overview]
Message-ID: <20250715034320.2553837-3-jacky_chou@aspeedtech.com> (raw)
In-Reply-To: <20250715034320.2553837-1-jacky_chou@aspeedtech.com>
This PHY is used by many modules. In our design, our
PCIe has RC and EP funcitons. On the different function,
each driver will use configure and get some information
from the PHY interface to do somting that it wants to.
Getting link status, setting syscon credits and so on.
Therefore, define it as syscon for all modules.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
---
.../bindings/soc/aspeed/aspeed,pcie-phy.yaml | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/aspeed/aspeed,pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/soc/aspeed/aspeed,pcie-phy.yaml b/Documentation/devicetree/bindings/soc/aspeed/aspeed,pcie-phy.yaml
new file mode 100644
index 000000000000..5fa585d63ca6
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/aspeed/aspeed,pcie-phy.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/aspeed/aspeed,pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED PCIe PHY
+
+maintainers:
+ - Jacky Chou <jacky_chou@aspeedtech.com>
+
+description:
+ The ASPEED PCIe PHY provides the physical layer interface for PCIe
+ controllers in the SoC. This node represents the register block for the PCIe
+ PHY, which is typically accessed by PCIe Root Complex or Endpoint drivers
+ via syscon. It is used to configure and get the status of the PCIe PHY
+ hardware, including power management, link training, and other PHY-specific
+ operations.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,pcie-phy
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@1e6ed200 {
+ compatible = "aspeed,pcie-phy", "syscon";
+ reg = <0x1e6ed200 0x100>;
+ };
--
2.43.0
next prev parent reply other threads:[~2025-07-15 4:08 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-15 3:43 [PATCH v2 00/10] Add ASPEED PCIe Root Complex support Jacky Chou
2025-07-15 3:43 ` [PATCH v2 01/10] dt-bindings: soc: aspeed: Add ASPEED PCIe Config support Jacky Chou
2025-07-16 8:24 ` Krzysztof Kozlowski
2025-07-21 3:47 ` 回覆: " Jacky Chou
2025-07-15 3:43 ` Jacky Chou [this message]
2025-07-16 8:23 ` [PATCH v2 02/10] dt-bindings: soc: aspeed: Add ASPEED PCIe PHY support Krzysztof Kozlowski
2025-07-15 3:43 ` [PATCH v2 03/10] dt-bindings: PCI: Add ASPEED PCIe RC support Jacky Chou
2025-07-16 8:27 ` Krzysztof Kozlowski
2025-07-21 3:44 ` 回覆: " Jacky Chou
2025-07-21 7:00 ` Krzysztof Kozlowski
2025-07-22 5:29 ` Jacky Chou
2025-07-15 3:43 ` [PATCH v2 04/10] dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# group Jacky Chou
2025-07-16 8:27 ` Krzysztof Kozlowski
2025-07-21 3:32 ` 回覆: " Jacky Chou
2025-07-15 3:43 ` [PATCH v2 05/10] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST# Jacky Chou
2025-07-15 3:43 ` [PATCH v2 06/10] ARM: dts: aspeed-g6: Add PCIe RC node Jacky Chou
2025-07-15 15:25 ` Rob Herring
2025-07-16 3:51 ` Jacky Chou
2025-07-20 22:22 ` Rob Herring
2025-07-21 3:21 ` 回覆: " Jacky Chou
2025-07-15 3:43 ` [PATCH v2 07/10] pinctrl: aspeed-g6: Add PCIe RC PERST pin group Jacky Chou
2025-07-23 11:23 ` Linus Walleij
2025-08-27 3:08 ` Jacky Chou
2025-08-28 20:46 ` Linus Walleij
2025-08-29 5:44 ` Jacky Chou
2025-07-15 3:43 ` [PATCH v2 08/10] PCI: Add FMT and TYPE definition for TLP header Jacky Chou
2025-07-15 15:41 ` Bjorn Helgaas
2025-08-27 1:22 ` Jacky Chou
2025-07-15 20:13 ` kernel test robot
2025-07-15 3:43 ` [PATCH v2 09/10] PCI: aspeed: Add ASPEED PCIe RC driver Jacky Chou
2025-07-15 13:51 ` Philipp Zabel
2025-08-21 7:22 ` Jacky Chou
2025-07-15 16:22 ` Bjorn Helgaas
2025-08-22 7:00 ` 回覆: " Jacky Chou
2025-08-22 15:36 ` Bjorn Helgaas
2025-08-27 3:35 ` Jacky Chou
2025-07-15 17:00 ` Markus Elfring
2025-08-27 3:45 ` Jacky Chou
2025-07-15 22:28 ` kernel test robot
2025-07-15 3:43 ` [PATCH v2 10/10] MAINTAINERS: " Jacky Chou
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