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From: Jacky Chou <jacky_chou@aspeedtech.com>
To: <bhelgaas@google.com>, <lpieralisi@kernel.org>,
	<kwilczynski@kernel.org>, <mani@kernel.org>, <robh@kernel.org>,
	<krzk+dt@kernel.org>, <conor+dt@kernel.org>, <joel@jms.id.au>,
	<andrew@codeconstruct.com.au>, <linux-aspeed@lists.ozlabs.org>,
	<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Cc: <openbmc@lists.ozlabs.org>, <linux-gpio@vger.kernel.org>,
	<linus.walleij@linaro.org>, <p.zabel@pengutronix.de>,
	<BMC-SW@aspeedtech.com>
Subject: [PATCH v2 06/10] ARM: dts: aspeed-g6: Add PCIe RC node
Date: Tue, 15 Jul 2025 11:43:16 +0800	[thread overview]
Message-ID: <20250715034320.2553837-7-jacky_chou@aspeedtech.com> (raw)
In-Reply-To: <20250715034320.2553837-1-jacky_chou@aspeedtech.com>

The AST2600 has one PCIe RC, and add the relative configure regmap.

Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
---
 arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 61 +++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
index 8ed715bd53aa..ed99780b6860 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
@@ -379,6 +379,67 @@ rng: hwrng@1e6e2524 {
 				quality = <100>;
 			};
 
+			pcie_phy1: syscon@1e6ed200 {
+				compatible = "aspeed,pcie-phy", "syscon";
+				reg = <0x1e6ed200 0x100>;
+			};
+
+			pcie_cfg: syscon@1e770000 {
+				compatible = "aspeed,pcie-cfg", "syscon";
+				reg = <0x1e770000 0x80>;
+			};
+
+			pcie0: pcie@1e7700c0 {
+				compatible = "aspeed,ast2600-pcie";
+				device_type = "pci";
+				reg = <0x1e7700c0 0x40>;
+				linux,pci-domain = <0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+				bus-range = <0x80 0xff>;
+
+				ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000
+					  0x02000000 0x0 0x70000000 0x70000000 0x0 0x10000000>;
+
+				status = "disabled";
+
+				resets = <&syscon ASPEED_RESET_H2X>;
+				reset-names = "h2x";
+
+				#interrupt-cells = <1>;
+				msi-parent = <&pcie0>;
+				msi-controller;
+
+				aspeed,ahbc = <&ahbc>;
+				aspeed,pciecfg = <&pcie_cfg>;
+
+				interrupt-map-mask = <0 0 0 7>;
+				interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+						<0 0 0 2 &pcie_intc0 1>,
+						<0 0 0 3 &pcie_intc0 2>,
+						<0 0 0 4 &pcie_intc0 3>;
+				pcie_intc0: interrupt-controller {
+					interrupt-controller;
+					#address-cells = <0>;
+					#interrupt-cells = <1>;
+				};
+
+				pcie@8,0 {
+					reg = <0x804000 0 0 0 0>;
+					#address-cells = <3>;
+					#size-cells = <2>;
+					device_type = "pci";
+					resets = <&syscon ASPEED_RESET_PCIE_RC_O>;
+					reset-names = "perst";
+					clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
+					pinctrl-names = "default";
+					pinctrl-0 = <&pinctrl_pcierc1_default>;
+					aspeed,pciephy = <&pcie_phy1>;
+					ranges;
+				};
+			};
+
 			gfx: display@1e6e6000 {
 				compatible = "aspeed,ast2600-gfx", "syscon";
 				reg = <0x1e6e6000 0x1000>;
-- 
2.43.0



  parent reply	other threads:[~2025-07-15  4:18 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-15  3:43 [PATCH v2 00/10] Add ASPEED PCIe Root Complex support Jacky Chou
2025-07-15  3:43 ` [PATCH v2 01/10] dt-bindings: soc: aspeed: Add ASPEED PCIe Config support Jacky Chou
2025-07-16  8:24   ` Krzysztof Kozlowski
2025-07-21  3:47     ` 回覆: " Jacky Chou
2025-07-15  3:43 ` [PATCH v2 02/10] dt-bindings: soc: aspeed: Add ASPEED PCIe PHY support Jacky Chou
2025-07-16  8:23   ` Krzysztof Kozlowski
2025-07-15  3:43 ` [PATCH v2 03/10] dt-bindings: PCI: Add ASPEED PCIe RC support Jacky Chou
2025-07-16  8:27   ` Krzysztof Kozlowski
2025-07-21  3:44     ` 回覆: " Jacky Chou
2025-07-21  7:00       ` Krzysztof Kozlowski
2025-07-22  5:29         ` Jacky Chou
2025-07-15  3:43 ` [PATCH v2 04/10] dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# group Jacky Chou
2025-07-16  8:27   ` Krzysztof Kozlowski
2025-07-21  3:32     ` 回覆: " Jacky Chou
2025-07-15  3:43 ` [PATCH v2 05/10] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST# Jacky Chou
2025-07-15  3:43 ` Jacky Chou [this message]
2025-07-15 15:25   ` [PATCH v2 06/10] ARM: dts: aspeed-g6: Add PCIe RC node Rob Herring
2025-07-16  3:51     ` Jacky Chou
2025-07-20 22:22       ` Rob Herring
2025-07-21  3:21         ` 回覆: " Jacky Chou
2025-07-15  3:43 ` [PATCH v2 07/10] pinctrl: aspeed-g6: Add PCIe RC PERST pin group Jacky Chou
2025-07-23 11:23   ` Linus Walleij
2025-08-27  3:08     ` Jacky Chou
2025-08-28 20:46       ` Linus Walleij
2025-08-29  5:44         ` Jacky Chou
2025-07-15  3:43 ` [PATCH v2 08/10] PCI: Add FMT and TYPE definition for TLP header Jacky Chou
2025-07-15 15:41   ` Bjorn Helgaas
2025-08-27  1:22     ` Jacky Chou
2025-07-15 20:13   ` kernel test robot
2025-07-15  3:43 ` [PATCH v2 09/10] PCI: aspeed: Add ASPEED PCIe RC driver Jacky Chou
2025-07-15 13:51   ` Philipp Zabel
2025-08-21  7:22     ` Jacky Chou
2025-07-15 16:22   ` Bjorn Helgaas
2025-08-22  7:00     ` 回覆: " Jacky Chou
2025-08-22 15:36       ` Bjorn Helgaas
2025-08-27  3:35         ` Jacky Chou
2025-07-15 17:00   ` Markus Elfring
2025-08-27  3:45     ` Jacky Chou
2025-07-15 22:28   ` kernel test robot
2025-07-15  3:43 ` [PATCH v2 10/10] MAINTAINERS: " Jacky Chou

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