From: Krzysztof Kozlowski <krzk@kernel.org>
To: Jacky Chou <jacky_chou@aspeedtech.com>
Cc: bhelgaas@google.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, joel@jms.id.au,
andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org,
linux-gpio@vger.kernel.org, linus.walleij@linaro.org,
p.zabel@pengutronix.de, BMC-SW@aspeedtech.com
Subject: Re: [PATCH v2 01/10] dt-bindings: soc: aspeed: Add ASPEED PCIe Config support
Date: Wed, 16 Jul 2025 10:24:27 +0200 [thread overview]
Message-ID: <20250716-wine-partridge-of-wonder-af10a6@krzk-bin> (raw)
In-Reply-To: <20250715034320.2553837-2-jacky_chou@aspeedtech.com>
On Tue, Jul 15, 2025 at 11:43:11AM +0800, Jacky Chou wrote:
> +maintainers:
> + - Jacky Chou <jacky_chou@aspeedtech.com>
> +
> +description: |
Drop |
> + The ASPEED PCIe configuration syscon block provides a set of registers shared
> + by multiple PCIe-related devices within the SoC. This node represents the
> + common configuration space that allows these devices to coordinate and manage
> + shared PCIe settings, including address mapping, control, and status
> + registers. The syscon interface enables for various PCIe devices to access
> + and modify these shared registers in a consistent and centralized manner.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - aspeed,pcie-cfg
NAK, see writing bindings. You already received comments about generic
compatible in the past.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-07-16 8:43 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-15 3:43 [PATCH v2 00/10] Add ASPEED PCIe Root Complex support Jacky Chou
2025-07-15 3:43 ` [PATCH v2 01/10] dt-bindings: soc: aspeed: Add ASPEED PCIe Config support Jacky Chou
2025-07-16 8:24 ` Krzysztof Kozlowski [this message]
2025-07-21 3:47 ` 回覆: " Jacky Chou
2025-07-15 3:43 ` [PATCH v2 02/10] dt-bindings: soc: aspeed: Add ASPEED PCIe PHY support Jacky Chou
2025-07-16 8:23 ` Krzysztof Kozlowski
2025-07-15 3:43 ` [PATCH v2 03/10] dt-bindings: PCI: Add ASPEED PCIe RC support Jacky Chou
2025-07-16 8:27 ` Krzysztof Kozlowski
2025-07-21 3:44 ` 回覆: " Jacky Chou
2025-07-21 7:00 ` Krzysztof Kozlowski
2025-07-22 5:29 ` Jacky Chou
2025-07-15 3:43 ` [PATCH v2 04/10] dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# group Jacky Chou
2025-07-16 8:27 ` Krzysztof Kozlowski
2025-07-21 3:32 ` 回覆: " Jacky Chou
2025-07-15 3:43 ` [PATCH v2 05/10] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST# Jacky Chou
2025-07-15 3:43 ` [PATCH v2 06/10] ARM: dts: aspeed-g6: Add PCIe RC node Jacky Chou
2025-07-15 15:25 ` Rob Herring
2025-07-16 3:51 ` Jacky Chou
2025-07-20 22:22 ` Rob Herring
2025-07-21 3:21 ` 回覆: " Jacky Chou
2025-07-15 3:43 ` [PATCH v2 07/10] pinctrl: aspeed-g6: Add PCIe RC PERST pin group Jacky Chou
2025-07-23 11:23 ` Linus Walleij
2025-08-27 3:08 ` Jacky Chou
2025-08-28 20:46 ` Linus Walleij
2025-08-29 5:44 ` Jacky Chou
2025-07-15 3:43 ` [PATCH v2 08/10] PCI: Add FMT and TYPE definition for TLP header Jacky Chou
2025-07-15 15:41 ` Bjorn Helgaas
2025-08-27 1:22 ` Jacky Chou
2025-07-15 20:13 ` kernel test robot
2025-07-15 3:43 ` [PATCH v2 09/10] PCI: aspeed: Add ASPEED PCIe RC driver Jacky Chou
2025-07-15 13:51 ` Philipp Zabel
2025-08-21 7:22 ` Jacky Chou
2025-07-15 16:22 ` Bjorn Helgaas
2025-08-22 7:00 ` 回覆: " Jacky Chou
2025-08-22 15:36 ` Bjorn Helgaas
2025-08-27 3:35 ` Jacky Chou
2025-07-15 17:00 ` Markus Elfring
2025-08-27 3:45 ` Jacky Chou
2025-07-15 22:28 ` kernel test robot
2025-07-15 3:43 ` [PATCH v2 10/10] MAINTAINERS: " Jacky Chou
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