From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A79ADC87FC5 for ; Mon, 21 Jul 2025 09:27:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=qORRuIce4CgG44+z6rN5TQu19ZSWx7jnn0vkZH9g2fU=; b=bFGS4po/rYDrlzvmZqQiasRHxm xCHafUBEktTtWjN0z2PCj/nq1i/VR5JTB/DsLpesdVEvXAI+tzLxBjbMce5Aw2Gkpe4Ux8ESpQucQ vPYywCYMq0qaJR/MattriSk/CePfxJj8yq2OkMLlGjQvsdrg/mh23giLJTqNfnpBPCgUiZYnCBETv D/3oIB8rK2kg1algTk11Wqsg8Yt9JV1lDv0HCXzK0LoR7gEE84H0ZTja1nWnScu49xImJv2+YpQNN bnQLkGfql8Aoad7hjS5AQqpxIeY4iuAY4PIMCcSe9VO9wmGH225qSpbxxpbQ8GO9lGbitvqbFENdE cid0EM4A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1udmoK-0000000Go9B-27RJ; Mon, 21 Jul 2025 09:27:52 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1udm0r-0000000GgHh-1Wce for linux-arm-kernel@lists.infradead.org; Mon, 21 Jul 2025 08:36:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1F56E153B; Mon, 21 Jul 2025 01:36:39 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2758F3F66E; Mon, 21 Jul 2025 01:36:43 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, ardb@kernel.org, frederic@kernel.org, james.morse@arm.com, joey.gouly@arm.com, scott@os.amperecomputing.com, maz@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH v4 6/7] arm64/asm: introduce lsui.h Date: Mon, 21 Jul 2025 09:36:17 +0100 Message-Id: <20250721083618.2743569-7-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250721083618.2743569-1-yeoreum.yun@arm.com> References: <20250721083618.2743569-1-yeoreum.yun@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250721_013645_448687_D701C041 X-CRM114-Status: GOOD ( 11.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch introduces lsui.h header file for applying runtime patch to use load/store unprevileged instructions when cpu supports FEAT_LSUI otherwise uses method implemented via ll/sc way with clearing PSTATE.PAN bit Signed-off-by: Yeoreum Yun --- arch/arm64/include/asm/lsui.h | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 arch/arm64/include/asm/lsui.h diff --git a/arch/arm64/include/asm/lsui.h b/arch/arm64/include/asm/lsui.h new file mode 100644 index 000000000000..39bf232f3eb7 --- /dev/null +++ b/arch/arm64/include/asm/lsui.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Arm Ltd. + */ +#ifndef __ASM_LSUI_H +#define __ASM_LSUI_H + +#define LL_SC_MAX_LOOPS 128 /* What's the largest number you can think of? */ + +#include + +#ifdef CONFIG_AS_HAS_LSUI + +#define __LSUI_PREAMBLE ".arch_extension lsui\n" + +#include +#include +#include +#include +#include +#include + +#include + +#define __lsui_ll_sc_u_body(op, ...) \ +({ \ + alternative_has_cap_likely(ARM64_HAS_LSUI) ? \ + __lsui_##op(__VA_ARGS__) : \ + __ll_sc_u_##op(__VA_ARGS__); \ +}) + +#else /* CONFIG_AS_HAS_LSUI */ + +#define __lsui_ll_sc_u_body(op, ...) __ll_sc_u_##op(__VA_ARGS__) + +#endif /* CONFIG_AS_HAS_LSUI */ +#endif /* __ASM_LSUI_H */ -- LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}