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From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	kvm@vger.kernel.org
Cc: Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>, Will Deacon <will@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>
Subject: [PATCH 1/7] arm64: Add capability denoting FEAT_RASv1p1
Date: Mon, 21 Jul 2025 11:19:49 +0100	[thread overview]
Message-ID: <20250721101955.535159-2-maz@kernel.org> (raw)
In-Reply-To: <20250721101955.535159-1-maz@kernel.org>

Detecting FEAT_RASv1p1 is rather complicated, as there are two
ways for the architecture to advertise the same thing (always a
delight...).

Add a capability that will advertise this in a synthetic way to
the rest of the kernel.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/kernel/cpufeature.c | 24 ++++++++++++++++++++++++
 arch/arm64/tools/cpucaps       |  1 +
 2 files changed, 25 insertions(+)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index a40b94f8e14e1..2da246b593ff7 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2235,6 +2235,24 @@ static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
 	/* Firmware may have left a deferred SError in this register. */
 	write_sysreg_s(0, SYS_DISR_EL1);
 }
+static bool has_rasv1p1(const struct arm64_cpu_capabilities *__unused, int scope)
+{
+	const struct arm64_cpu_capabilities rasv1p1_caps[] = {
+		{
+			ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, V1P1)
+		},
+		{
+			ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP)
+		},
+		{
+			ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, RAS_frac, RASv1p1)
+		},
+	};
+
+	return (has_cpuid_feature(&rasv1p1_caps[0], scope) ||
+		(has_cpuid_feature(&rasv1p1_caps[1], scope) &&
+		 has_cpuid_feature(&rasv1p1_caps[2], scope)));
+}
 #endif /* CONFIG_ARM64_RAS_EXTN */
 
 #ifdef CONFIG_ARM64_PTR_AUTH
@@ -2653,6 +2671,12 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.cpu_enable = cpu_clear_disr,
 		ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP)
 	},
+	{
+		.desc = "RASv1p1 Extension Support",
+		.capability = ARM64_HAS_RASV1P1_EXTN,
+		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
+		.matches = has_rasv1p1,
+	},
 #endif /* CONFIG_ARM64_RAS_EXTN */
 #ifdef CONFIG_ARM64_AMU_EXTN
 	{
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index 115161dd9a24d..eb7f1f5622a8f 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -52,6 +52,7 @@ HAS_S1PIE
 HAS_S1POE
 HAS_SCTLR2
 HAS_RAS_EXTN
+HAS_RASV1P1_EXTN
 HAS_RNG
 HAS_SB
 HAS_STAGE2_FWB
-- 
2.39.2



  reply	other threads:[~2025-07-21 11:39 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-21 10:19 [PATCH 0/7] KVM: arm64: FEAT_RASv1p1 support and RAS selection Marc Zyngier
2025-07-21 10:19 ` Marc Zyngier [this message]
2025-07-21 13:52   ` [PATCH 1/7] arm64: Add capability denoting FEAT_RASv1p1 Catalin Marinas
2025-07-21 10:19 ` [PATCH 2/7] KVM: arm64: Filter out HCR_EL2 bits when running in hypervisor context Marc Zyngier
2025-07-21 10:19 ` [PATCH 3/7] KVM: arm64: Make RAS registers UNDEF when RAS isn't advertised Marc Zyngier
2025-07-21 10:19 ` [PATCH 4/7] KVM: arm64: Handle RASv1p1 registers Marc Zyngier
2025-07-21 13:08   ` Marc Zyngier
2025-07-21 10:19 ` [PATCH 5/7] KVM: arm64: Ignore HCR_EL2.FIEN set by L1 guest's EL2 Marc Zyngier
2025-07-21 10:19 ` [PATCH 6/7] KVM: arm64: Expose FEAT_RASv1p1 in a canonical manner Marc Zyngier
2025-07-21 12:32   ` Cornelia Huck
2025-07-21 12:55     ` Marc Zyngier
2025-07-21 13:12       ` Cornelia Huck
2025-07-21 13:33         ` Marc Zyngier
2025-07-21 10:19 ` [PATCH 7/7] KVM: arm64: Make ID_AA64PFR0_EL1.RAS writable Marc Zyngier
2025-07-21 22:24 ` (subset) [PATCH 0/7] KVM: arm64: FEAT_RASv1p1 support and RAS selection Oliver Upton

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