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From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	kvm@vger.kernel.org
Cc: Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>, Will Deacon <will@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>
Subject: [PATCH 6/7] KVM: arm64: Expose FEAT_RASv1p1 in a canonical manner
Date: Mon, 21 Jul 2025 11:19:54 +0100	[thread overview]
Message-ID: <20250721101955.535159-7-maz@kernel.org> (raw)
In-Reply-To: <20250721101955.535159-1-maz@kernel.org>

If we have RASv1p1 on the host, advertise it to the guest in the
"canonical way", by setting ID_AA64PFR0_EL1 to V1P1, rather than
the convoluted RAS+RAS_frac method.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/kvm/sys_regs.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 9fb2812106cb0..549766d7abca8 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1800,6 +1800,15 @@ static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val)
 	if (!vcpu_has_sve(vcpu))
 		val &= ~ID_AA64PFR0_EL1_SVE_MASK;
 
+	/*
+	 * Describe RASv1p1 in a canonical way -- ID_AA64PFR1_EL1.RAS_frac
+	 * is cleared separately.
+	 */
+	if (cpus_have_final_cap(ARM64_HAS_RASV1P1_EXTN)) {
+		val &= ~ID_AA64PFR0_EL1_RAS;
+		val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, RAS, V1P1);
+	}
+
 	/*
 	 * The default is to expose CSV2 == 1 if the HW isn't affected.
 	 * Although this is a per-CPU feature, we make it global because
-- 
2.39.2



  parent reply	other threads:[~2025-07-21 11:39 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-21 10:19 [PATCH 0/7] KVM: arm64: FEAT_RASv1p1 support and RAS selection Marc Zyngier
2025-07-21 10:19 ` [PATCH 1/7] arm64: Add capability denoting FEAT_RASv1p1 Marc Zyngier
2025-07-21 13:52   ` Catalin Marinas
2025-07-21 10:19 ` [PATCH 2/7] KVM: arm64: Filter out HCR_EL2 bits when running in hypervisor context Marc Zyngier
2025-07-21 10:19 ` [PATCH 3/7] KVM: arm64: Make RAS registers UNDEF when RAS isn't advertised Marc Zyngier
2025-07-21 10:19 ` [PATCH 4/7] KVM: arm64: Handle RASv1p1 registers Marc Zyngier
2025-07-21 13:08   ` Marc Zyngier
2025-07-21 10:19 ` [PATCH 5/7] KVM: arm64: Ignore HCR_EL2.FIEN set by L1 guest's EL2 Marc Zyngier
2025-07-21 10:19 ` Marc Zyngier [this message]
2025-07-21 12:32   ` [PATCH 6/7] KVM: arm64: Expose FEAT_RASv1p1 in a canonical manner Cornelia Huck
2025-07-21 12:55     ` Marc Zyngier
2025-07-21 13:12       ` Cornelia Huck
2025-07-21 13:33         ` Marc Zyngier
2025-07-21 10:19 ` [PATCH 7/7] KVM: arm64: Make ID_AA64PFR0_EL1.RAS writable Marc Zyngier
2025-07-21 22:24 ` (subset) [PATCH 0/7] KVM: arm64: FEAT_RASv1p1 support and RAS selection Oliver Upton

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