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From: Leo Yan <leo.yan@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
	 Mike Leach <mike.leach@linaro.org>,
	James Clark <james.clark@linaro.org>,
	 Anshuman Khandual <anshuman.khandual@arm.com>,
	 Yeoreum Yun <yeoreum.yun@arm.com>,
	 Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	 Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
	 linux-kernel@vger.kernel.org, Leo Yan <leo.yan@arm.com>
Subject: [PATCH v5 01/10] coresight: tmc: Support atclk
Date: Thu, 24 Jul 2025 16:22:31 +0100	[thread overview]
Message-ID: <20250724-arm_cs_fix_clock_v4-v5-1-63f648dae021@arm.com> (raw)
In-Reply-To: <20250724-arm_cs_fix_clock_v4-v5-0-63f648dae021@arm.com>

The atclk is an optional clock for the CoreSight TMC, but the driver
misses to initialize it.  In most cases, TMC shares the atclk clock with
other CoreSight components.  Since these components enable the clock
before the TMC device is initialized, the TMC continues properly,
which is why we don’t observe any lockup issues.

This change enables atclk in probe of the TMC driver.  Given the clock
is optional, it is possible to return NULL if the clock does not exist.
IS_ERR() is tolerant for this case.

Dynamically disable and enable atclk during suspend and resume.  The
clock pointers will never be error values if the driver has successfully
probed, and the case of a NULL pointer case will be handled by the clock
core layer.  The driver data is always valid after probe. Therefore,
remove the related checks.  Also in the resume flow adds error handling.

Fixes: bc4bf7fe98da ("coresight-tmc: add CoreSight TMC driver")
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Yeoreum Yun <yeoreum.yun@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc-core.c | 22 +++++++++++++++++-----
 drivers/hwtracing/coresight/coresight-tmc.h      |  2 ++
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
index be964656be9335f1b74277ba4e012ab8d6ed1785..85ba037c27f7b18fd4aed2447129f15316e635d5 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-core.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
@@ -779,6 +779,10 @@ static int __tmc_probe(struct device *dev, struct resource *res)
 	struct coresight_desc desc = { 0 };
 	struct coresight_dev_list *dev_list = NULL;
 
+	drvdata->atclk = devm_clk_get_optional_enabled(dev, "atclk");
+	if (IS_ERR(drvdata->atclk))
+		return PTR_ERR(drvdata->atclk);
+
 	ret = -ENOMEM;
 
 	/* Validity for the resource is already checked by the AMBA core */
@@ -1010,18 +1014,26 @@ static int tmc_runtime_suspend(struct device *dev)
 {
 	struct tmc_drvdata *drvdata = dev_get_drvdata(dev);
 
-	if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
-		clk_disable_unprepare(drvdata->pclk);
+	clk_disable_unprepare(drvdata->atclk);
+	clk_disable_unprepare(drvdata->pclk);
+
 	return 0;
 }
 
 static int tmc_runtime_resume(struct device *dev)
 {
 	struct tmc_drvdata *drvdata = dev_get_drvdata(dev);
+	int ret;
 
-	if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
-		clk_prepare_enable(drvdata->pclk);
-	return 0;
+	ret = clk_prepare_enable(drvdata->pclk);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(drvdata->atclk);
+	if (ret)
+		clk_disable_unprepare(drvdata->pclk);
+
+	return ret;
 }
 #endif
 
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 6541a27a018e6c3da8685e2e1c93b228d44e66fc..cbb4ba43915855a8acbb9205167e87185c9a8c6c 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -210,6 +210,7 @@ struct tmc_resrv_buf {
 
 /**
  * struct tmc_drvdata - specifics associated to an TMC component
+ * @atclk:	optional clock for the core parts of the TMC.
  * @pclk:	APB clock if present, otherwise NULL
  * @base:	memory mapped base address for this component.
  * @csdev:	component vitals needed by the framework.
@@ -244,6 +245,7 @@ struct tmc_resrv_buf {
  *		 Used by ETR/ETF.
  */
 struct tmc_drvdata {
+	struct clk		*atclk;
 	struct clk		*pclk;
 	void __iomem		*base;
 	struct coresight_device	*csdev;

-- 
2.34.1



  reply	other threads:[~2025-07-24 17:05 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-24 15:22 [PATCH v5 00/10] coresight: Fix and improve clock usage Leo Yan
2025-07-24 15:22 ` Leo Yan [this message]
2025-07-24 15:22 ` [PATCH v5 02/10] coresight: catu: Support atclk Leo Yan
2025-07-24 15:22 ` [PATCH v5 03/10] coresight: etm4x: " Leo Yan
2025-07-24 15:22 ` [PATCH v5 04/10] coresight: Appropriately disable programming clocks Leo Yan
2025-07-28 16:18   ` Mark Brown
2025-07-28 16:44   ` Mark Brown
2025-07-29 11:31     ` Mark Brown
2025-07-29 12:30       ` Suzuki K Poulose
2025-07-30  8:56         ` Leo Yan
2025-07-30  9:27           ` Suzuki K Poulose
2025-07-30 10:54             ` Leo Yan
2025-07-30 11:01               ` Suzuki K Poulose
2025-07-30 11:09                 ` Mark Brown
2025-07-30 17:57                   ` Leo Yan
2025-07-24 15:22 ` [PATCH v5 05/10] coresight: Appropriately disable trace bus clocks Leo Yan
2025-07-24 15:22 ` [PATCH v5 06/10] coresight: Avoid enable programming clock duplicately Leo Yan
2025-07-24 15:22 ` [PATCH v5 07/10] coresight: Consolidate clock enabling Leo Yan
2025-07-24 15:22 ` [PATCH v5 08/10] coresight: Refactor driver data allocation Leo Yan
2025-07-24 15:22 ` [PATCH v5 09/10] coresight: Make clock sequence consistent Leo Yan
2025-07-24 15:22 ` [PATCH v5 10/10] coresight: Refactor runtime PM Leo Yan
2025-07-25  8:45 ` [PATCH v5 00/10] coresight: Fix and improve clock usage James Clark
2025-07-25  9:22 ` Suzuki K Poulose
2025-07-29 12:31   ` Suzuki K Poulose

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