[PATCH v2 0/7] porting pq compnent for MT8196

[PATCH v2 0/7] porting pq compnent for MT8196

[Jay Liu]

From: 20220315152503 created <jay.liu@mediatek.com>

add ccorr/dither/gamma/tdshp support for MT8196

Change in v2:
- Modify the ccorr driver code to optimize the ctm_set process and avoid affecting other ICs.
- Modify the tdshp driver code to remove unnecessary code.
- Update the dt-bindings of tdshp, including clocks, description, examples, etc.

This patch series id base on [1]
[1] Add components to support PQ in display path for MT8196
    - https://patchwork.kernel.org/project/linux-mediatek/list/?series=955361
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Jay Liu (7):
  drm/mediatek: Add CCORR component support for MT8196
  drm/mediatek: fix CCORR mtk_ctm_s31_32_to_s1_n function issue
  drm/mediatek: Add TDSHP component support for MT8196
  dt-bindings: display: mediatek: disp-tdshp: Add support for MT8196
  dt-bindings: display: mediatek: ccorr: Add support for MT8196
  dt-bindings: display: mediatek: dither: Add support for MT8196
  dt-bindings: display: mediatek: gamma: Add support for MT8196

 .../display/mediatek/mediatek,ccorr.yaml      |  1 +
 .../display/mediatek/mediatek,disp-tdshp.yaml | 50 ++++++++++++++++++
 .../display/mediatek/mediatek,dither.yaml     |  1 +
 .../display/mediatek/mediatek,gamma.yaml      |  1 +
 drivers/gpu/drm/mediatek/mtk_crtc.c           |  5 +-
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c       | 52 ++++++++++++++++++-
 drivers/gpu/drm/mediatek/mtk_ddp_comp.h       |  8 +--
 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c     | 30 +++--------
 drivers/gpu/drm/mediatek/mtk_disp_drv.h       |  2 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  2 +
 10 files changed, 122 insertions(+), 30 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml

-- 
2.46.0

[PATCH v2 1/7] drm/mediatek: Add CCORR component support for MT8196

[Jay Liu]

Add CCORR component support for MT8196.

CCORR is a hardware module that optimizes the visual effects of
images by adjusting the color matrix, enabling features such as
night light.

The 8196 SoC has two CCORR hardware units, which must be chained
together in a fixed order in the display path to display the image
correctly. the `mtk_ccorr_ctm_set` API only utilizes one of these units.
To prevent the unused CCORR unit from inadvertently taking effect,
we need to block it in the mtk_crtc.c.

Signed-off-by: Jay Liu <jay.liu@mediatek.com>
Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_crtc.c       | 5 ++++-
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c   | 3 ++-
 drivers/gpu/drm/mediatek/mtk_ddp_comp.h   | 7 ++++---
 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 ++++--
 drivers/gpu/drm/mediatek/mtk_disp_drv.h   | 2 +-
 5 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek/mtk_crtc.c
index bc7527542fdc..6b9cb52e9207 100644
--- a/drivers/gpu/drm/mediatek/mtk_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_crtc.c
@@ -859,11 +859,14 @@ static void mtk_crtc_atomic_flush(struct drm_crtc *crtc,
 {
 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
 	int i;
+	bool ctm_set = false;
 
 	if (crtc->state->color_mgmt_changed)
 		for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 			mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
-			mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
+			/* only set ctm once for the pipeline with two CCORR components */
+			if (!ctm_set)
+				ctm_set = mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
 		}
 	mtk_crtc_update_config(mtk_crtc, !!mtk_crtc->event);
 }
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index ac6620e10262..850e3b18da61 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -458,7 +458,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
 	[DDP_COMPONENT_AAL0]		= { MTK_DISP_AAL,		0, &ddp_aal },
 	[DDP_COMPONENT_AAL1]		= { MTK_DISP_AAL,		1, &ddp_aal },
 	[DDP_COMPONENT_BLS]		= { MTK_DISP_BLS,		0, NULL },
-	[DDP_COMPONENT_CCORR]		= { MTK_DISP_CCORR,		0, &ddp_ccorr },
+	[DDP_COMPONENT_CCORR0]		= { MTK_DISP_CCORR,		0, &ddp_ccorr },
+	[DDP_COMPONENT_CCORR1]		= { MTK_DISP_CCORR,		1, &ddp_ccorr },
 	[DDP_COMPONENT_COLOR0]		= { MTK_DISP_COLOR,		0, &ddp_color },
 	[DDP_COMPONENT_COLOR1]		= { MTK_DISP_COLOR,		1, &ddp_color },
 	[DDP_COMPONENT_DITHER0]		= { MTK_DISP_DITHER,		0, &ddp_dither },
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index 7289b3dcf22f..98a701ac4cde 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -77,7 +77,7 @@ struct mtk_ddp_comp_funcs {
 			  struct drm_crtc_state *state);
 	void (*bgclr_in_on)(struct device *dev);
 	void (*bgclr_in_off)(struct device *dev);
-	void (*ctm_set)(struct device *dev,
+	bool (*ctm_set)(struct device *dev,
 			struct drm_crtc_state *state);
 	struct device * (*dma_dev_get)(struct device *dev);
 	u32 (*get_blend_modes)(struct device *dev);
@@ -254,11 +254,12 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
 		comp->funcs->bgclr_in_off(comp->dev);
 }
 
-static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
+static inline bool mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
 				   struct drm_crtc_state *state)
 {
 	if (comp->funcs && comp->funcs->ctm_set)
-		comp->funcs->ctm_set(comp->dev, state);
+		return comp->funcs->ctm_set(comp->dev, state);
+	return false;
 }
 
 static inline struct device *mtk_ddp_comp_dma_dev_get(struct mtk_ddp_comp *comp)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
index 10d60d2c2a56..85ba109d6383 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -101,7 +101,7 @@ static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n)
 	return r;
 }
 
-void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
+bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
 {
 	struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
 	struct drm_property_blob *blob = state->ctm;
@@ -113,7 +113,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
 	u32 matrix_bits = ccorr->data->matrix_bits;
 
 	if (!blob)
-		return;
+		return false;
 
 	ctm = (struct drm_color_ctm *)blob->data;
 	input = ctm->matrix;
@@ -131,6 +131,8 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
 		      &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3);
 	mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
 		      &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4);
+
+	return true;
 }
 
 static int mtk_disp_ccorr_bind(struct device *dev, struct device *master,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 679d413bf10b..4203c28c38ce 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -22,7 +22,7 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state);
 void mtk_aal_start(struct device *dev);
 void mtk_aal_stop(struct device *dev);
 
-void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state);
+bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state);
 int mtk_ccorr_clk_enable(struct device *dev);
 void mtk_ccorr_clk_disable(struct device *dev);
 void mtk_ccorr_config(struct device *dev, unsigned int w,
-- 
2.46.0

[PATCH v2 2/7] drm/mediatek: fix CCORR mtk_ctm_s31_32_to_s1_n function issue

[Jay Liu]

if matrixbit is 11,
The range of color matrix is from 0 to (BIT(12) - 1).
Values from 0 to (BIT(11) - 1) represent positive numbers,
values from BIT(11) to (BIT(12) - 1) represent negative numbers.
For example, -1 need converted to 8191.
so convert S31.32 to HW Q2.11 format by drm_color_ctm_s31_32_to_qm_n,
and set int_bits to 2.

Fixes: 738ed4156fba ("drm/mediatek: Add matrix_bits private data for ccorr")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Jay Liu <jay.liu@mediatek.com>
Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 24 ++---------------------
 1 file changed, 2 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
index 85ba109d6383..b097c20877f3 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -80,27 +80,6 @@ void mtk_ccorr_stop(struct device *dev)
 	writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
 }
 
-/* Converts a DRM S31.32 value to the HW S1.n format. */
-static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n)
-{
-	u16 r;
-
-	/* Sign bit. */
-	r = in & BIT_ULL(63) ? BIT(n + 1) : 0;
-
-	if ((in & GENMASK_ULL(62, 33)) > 0) {
-		/* identity value 0x100000000 -> 0x400(mt8183), */
-		/* identity value 0x100000000 -> 0x800(mt8192), */
-		/* if bigger this, set it to max 0x7ff. */
-		r |= GENMASK(n, 0);
-	} else {
-		/* take the n+1 most important bits. */
-		r |= (in >> (32 - n)) & GENMASK(n, 0);
-	}
-
-	return r;
-}
-
 bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
 {
 	struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
@@ -109,6 +88,7 @@ bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
 	const u64 *input;
 	uint16_t coeffs[9] = { 0 };
 	int i;
+	int int_bits = 2;
 	struct cmdq_pkt *cmdq_pkt = NULL;
 	u32 matrix_bits = ccorr->data->matrix_bits;
 
@@ -119,7 +99,7 @@ bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
 	input = ctm->matrix;
 
 	for (i = 0; i < ARRAY_SIZE(coeffs); i++)
-		coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits);
+		coeffs[i] = drm_color_ctm_s31_32_to_qm_n(input[i], int_bits, matrix_bits);
 
 	mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
 		      &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0);
-- 
2.46.0

[PATCH v2 3/7] drm/mediatek: Add TDSHP component support for MT8196

[Jay Liu]

Add TDSHP component support for MT8196.
TDSHP is a hardware module designed to enhance the sharpness and
clarity of displayed images by analyzing and improving edges and
fine details in frames.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Jay Liu <jay.liu@mediatek.com>
Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 49 +++++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  2 +
 3 files changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index 850e3b18da61..c63a12c41215 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -57,6 +57,14 @@
 #define POSTMASK_RELAY_MODE				BIT(0)
 #define DISP_REG_POSTMASK_SIZE			0x0030
 
+#define DISP_REG_TDSHP_CTRL			0x0100
+#define DISP_TDSHP_CTRL_EN			BIT(0)
+#define DISP_REG_TDSHP_CFG			0x0110
+#define DISP_TDSHP_RELAY_MODE			BIT(0)
+#define DISP_REG_TDSHP_INPUT_SIZE		0x0120
+#define DISP_REG_TDSHP_OUTPUT_OFFSET		0x0124
+#define DISP_REG_TDSHP_OUTPUT_SIZE		0x0128
+
 #define DISP_REG_UFO_START			0x0000
 #define UFO_BYPASS				BIT(2)
 
@@ -261,6 +269,37 @@ static void mtk_postmask_stop(struct device *dev)
 	writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
 }
 
+static void mtk_disp_tdshp_config(struct device *dev, unsigned int w,
+				  unsigned int h, unsigned int vrefresh,
+				  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_TDSHP_INPUT_SIZE);
+	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_TDSHP_OUTPUT_SIZE);
+	mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_TDSHP_OUTPUT_OFFSET);
+
+	mtk_ddp_write(cmdq_pkt, DISP_TDSHP_RELAY_MODE, &priv->cmdq_reg,
+		      priv->regs, DISP_REG_TDSHP_CFG);
+}
+
+static void mtk_disp_tdshp_start(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel(DISP_TDSHP_CTRL_EN, priv->regs + DISP_REG_TDSHP_CTRL);
+}
+
+static void mtk_disp_tdshp_stop(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel(0, priv->regs + DISP_REG_TDSHP_CTRL);
+}
+
 static void mtk_ufoe_start(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
@@ -268,6 +307,14 @@ static void mtk_ufoe_start(struct device *dev)
 	writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
 }
 
+static const struct mtk_ddp_comp_funcs ddp_tdshp = {
+	.clk_enable = mtk_ddp_clk_enable,
+	.clk_disable = mtk_ddp_clk_disable,
+	.config = mtk_disp_tdshp_config,
+	.start = mtk_disp_tdshp_start,
+	.stop = mtk_disp_tdshp_stop,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_aal = {
 	.clk_enable = mtk_aal_clk_enable,
 	.clk_disable = mtk_aal_clk_disable,
@@ -441,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_POSTMASK] = "postmask",
 	[MTK_DISP_PWM] = "pwm",
 	[MTK_DISP_RDMA] = "rdma",
+	[MTK_DISP_TDSHP] = "tdshp",
 	[MTK_DISP_UFOE] = "ufoe",
 	[MTK_DISP_WDMA] = "wdma",
 	[MTK_DP_INTF] = "dp-intf",
@@ -496,6 +544,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
 	[DDP_COMPONENT_RDMA1]		= { MTK_DISP_RDMA,		1, &ddp_rdma },
 	[DDP_COMPONENT_RDMA2]		= { MTK_DISP_RDMA,		2, &ddp_rdma },
 	[DDP_COMPONENT_RDMA4]		= { MTK_DISP_RDMA,		4, &ddp_rdma },
+	[DDP_COMPONENT_TDSHP0]		= { MTK_DISP_TDSHP,		0, &ddp_tdshp },
 	[DDP_COMPONENT_UFOE]		= { MTK_DISP_UFOE,		0, &ddp_ufoe },
 	[DDP_COMPONENT_WDMA0]		= { MTK_DISP_WDMA,		0, NULL },
 	[DDP_COMPONENT_WDMA1]		= { MTK_DISP_WDMA,		1, NULL },
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index 98a701ac4cde..a03fa3385d2f 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -38,6 +38,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_POSTMASK,
 	MTK_DISP_PWM,
 	MTK_DISP_RDMA,
+	MTK_DISP_TDSHP,
 	MTK_DISP_UFOE,
 	MTK_DISP_WDMA,
 	MTK_DPI,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index d5e6bab36414..042cf03c7a54 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -812,6 +812,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8195-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8196-disp-tdshp",
+	  .data = (void *)MTK_DISP_TDSHP },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
 	  .data = (void *)MTK_DISP_UFOE },
 	{ .compatible = "mediatek,mt8173-disp-wdma",
-- 
2.46.0

[PATCH v2 4/7] dt-bindings: display: mediatek: disp-tdshp: Add support for MT8196

[Jay Liu]

Add disp-tdshp hardware description for MediaTek MT8196 SoC

Signed-off-by: Jay Liu <jay.liu@mediatek.com>
Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
---
 .../display/mediatek/mediatek,disp-tdshp.yaml | 50 +++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml
new file mode 100644
index 000000000000..3d95ecfc0d19
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,disp-tdshp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek display 2D sharpness processor
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  MediaTek display 2D sharpness processor, namely TDSHP, provides a
+  operation used to adjust sharpness in display system.
+  TDSHP device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+      - enum:
+          - mediatek,mt8196-disp-tdshp
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+additionalProperties: false
+
+examples:
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        disp-tdshp@321e0000 {
+            compatible = "mediatek,mt8196-disp-tdshp";
+            reg = <0 0x321e0000 0 0x1000>;
+            clocks = <&dispsys_config_clk 107>;
+        };
+    };
-- 
2.46.0

[PATCH v2 5/7] dt-bindings: display: mediatek: ccorr: Add support for MT8196

[Jay Liu]

Add a compatible string for the CCORR IP found in the MT8196 SoC.
Each CCORR IP of this SoC is fully compatible with the ones found
in MT8192.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Jay Liu <jay.liu@mediatek.com>
Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml     | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
index fca8e7bb0cbc..581003aa9b9c 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -32,6 +32,7 @@ properties:
               - mediatek,mt8186-disp-ccorr
               - mediatek,mt8188-disp-ccorr
               - mediatek,mt8195-disp-ccorr
+              - mediatek,mt8196-disp-ccorr
           - const: mediatek,mt8192-disp-ccorr
 
   reg:
-- 
2.46.0

[PATCH v2 6/7] dt-bindings: display: mediatek: dither: Add support for MT8196

[Jay Liu]

Add a compatible string for the DITHER IP found in the MT8196 SoC.
Each DITHER IP of this SoC is fully compatible with the ones found
in MT8183.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Jay Liu <jay.liu@mediatek.com>
Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,dither.yaml    | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
index abaf27916d13..1f1719228b5d 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
@@ -31,6 +31,7 @@ properties:
               - mediatek,mt8192-disp-dither
               - mediatek,mt8195-disp-dither
               - mediatek,mt8365-disp-dither
+              - mediatek,mt8196-disp-dither
           - const: mediatek,mt8183-disp-dither
 
   reg:
-- 
2.46.0

[PATCH v2 7/7] dt-bindings: display: mediatek: gamma: Add support for MT8196

[Jay Liu]

Add a compatible string for the GAMMA IP found in the MT8196 SoC.
Each GAMMA IP of this SoC is fully compatible with the ones found
in MT8195.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Jay Liu <jay.liu@mediatek.com>
Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml     | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
index 48542dc7e784..513e51c6d2b9 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
@@ -40,6 +40,7 @@ properties:
       - items:
           - enum:
               - mediatek,mt8188-disp-gamma
+              - mediatek,mt8196-disp-gamma
           - const: mediatek,mt8195-disp-gamma
 
   reg:
-- 
2.46.0

Re: [PATCH v2 4/7] dt-bindings: display: mediatek: disp-tdshp: Add support for MT8196

[Rob Herring (Arm)]

On Sun, 27 Jul 2025 15:15:54 +0800, Jay Liu wrote:
> Add disp-tdshp hardware description for MediaTek MT8196 SoC
> 
> Signed-off-by: Jay Liu <jay.liu@mediatek.com>
> Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
> ---
>  .../display/mediatek/mediatek,disp-tdshp.yaml | 50 +++++++++++++++++++
>  1 file changed, 50 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:
./Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml:23:7: [warning] wrong indentation: expected 4 but found 6 (indentation)
./Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml:41:5: [warning] wrong indentation: expected 2 but found 4 (indentation)
./Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml:42:10: [error] missing starting space in comment (comments)
./Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml:43:10: [error] missing starting space in comment (comments)
./Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml:45:9: [error] syntax error: expected <block end>, but found '<scalar>' (syntax)

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml: ignoring, error parsing file
./Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml:45:9: did not find expected key
make[2]: *** Deleting file 'Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.example.dts'
Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml:45:9: did not find expected key
make[2]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.example.dts] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1526: dt_binding_check] Error 2
make: *** [Makefile:248: __sub-make] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250727071609.26037-5-jay.liu@mediatek.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH v2 5/7] dt-bindings: display: mediatek: ccorr: Add support for MT8196

[Rob Herring (Arm)]

On Sun, 27 Jul 2025 15:15:55 +0800, Jay Liu wrote:
> Add a compatible string for the CCORR IP found in the MT8196 SoC.
> Each CCORR IP of this SoC is fully compatible with the ones found
> in MT8192.
> 
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: Jay Liu <jay.liu@mediatek.com>
> Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
> ---
>  .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml     | 1 +
>  1 file changed, 1 insertion(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:


doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250727071609.26037-6-jay.liu@mediatek.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH v2 6/7] dt-bindings: display: mediatek: dither: Add support for MT8196

[Rob Herring (Arm)]

On Sun, 27 Jul 2025 15:15:56 +0800, Jay Liu wrote:
> Add a compatible string for the DITHER IP found in the MT8196 SoC.
> Each DITHER IP of this SoC is fully compatible with the ones found
> in MT8183.
> 
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: Jay Liu <jay.liu@mediatek.com>
> Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
> ---
>  .../devicetree/bindings/display/mediatek/mediatek,dither.yaml    | 1 +
>  1 file changed, 1 insertion(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:


doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250727071609.26037-7-jay.liu@mediatek.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH v2 7/7] dt-bindings: display: mediatek: gamma: Add support for MT8196

[Rob Herring (Arm)]

On Sun, 27 Jul 2025 15:15:57 +0800, Jay Liu wrote:
> Add a compatible string for the GAMMA IP found in the MT8196 SoC.
> Each GAMMA IP of this SoC is fully compatible with the ones found
> in MT8195.
> 
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: Jay Liu <jay.liu@mediatek.com>
> Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
> ---
>  .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml     | 1 +
>  1 file changed, 1 insertion(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:


doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250727071609.26037-8-jay.liu@mediatek.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH v2 5/7] dt-bindings: display: mediatek: ccorr: Add support for MT8196

[Rob Herring]

On Sun, Jul 27, 2025 at 03:15:55PM +0800, Jay Liu wrote:
> Add a compatible string for the CCORR IP found in the MT8196 SoC.
> Each CCORR IP of this SoC is fully compatible with the ones found
> in MT8192.
> 
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: Jay Liu <jay.liu@mediatek.com>
> Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>

????

> ---
>  .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml     | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> index fca8e7bb0cbc..581003aa9b9c 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> @@ -32,6 +32,7 @@ properties:
>                - mediatek,mt8186-disp-ccorr
>                - mediatek,mt8188-disp-ccorr
>                - mediatek,mt8195-disp-ccorr
> +              - mediatek,mt8196-disp-ccorr
>            - const: mediatek,mt8192-disp-ccorr
>  
>    reg:
> -- 
> 2.46.0
> 

Re: [PATCH v2 5/7] dt-bindings: display: mediatek: ccorr: Add support for MT8196

[Jay Liu (刘博)]

On Sun, 2025-07-27 at 15:35 -0500, Rob Herring wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On Sun, Jul 27, 2025 at 03:15:55PM +0800, Jay Liu wrote:
> > Add a compatible string for the CCORR IP found in the MT8196 SoC.
> > Each CCORR IP of this SoC is fully compatible with the ones found
> > in MT8192.
> > 
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > Signed-off-by: Jay Liu <jay.liu@mediatek.com>
> > Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
> 
> ????
I will address this issues in next version
> > 
> > ---
> >  .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml     |
> > 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr
> > .yaml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr
> > .yaml
> > index fca8e7bb0cbc..581003aa9b9c 100644
> > ---
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr
> > .yaml
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr
> > .yaml
> > @@ -32,6 +32,7 @@ properties:
> >                - mediatek,mt8186-disp-ccorr
> >                - mediatek,mt8188-disp-ccorr
> >                - mediatek,mt8195-disp-ccorr
> > +              - mediatek,mt8196-disp-ccorr
> >            - const: mediatek,mt8192-disp-ccorr
> > 
> >    reg:
> > --
> > 2.46.0
> > 

> >  

Re: [PATCH v2 4/7] dt-bindings: display: mediatek: disp-tdshp: Add support for MT8196

[Krzysztof Kozlowski]

On 27/07/2025 09:15, Jay Liu wrote:
> Add disp-tdshp hardware description for MediaTek MT8196 SoC
> 
> Signed-off-by: Jay Liu <jay.liu@mediatek.com>
> Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>


Who is this person?

Test your bindings BEFORE you send them, not after. That's v2 so I don't
get why this is not tested at this point.


Best regards,
Krzysztof

Re: [PATCH v2 4/7] dt-bindings: display: mediatek: disp-tdshp: Add support for MT8196

[Jay Liu (刘博)]

On Mon, 2025-07-28 at 14:01 +0200, Krzysztof Kozlowski wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On 27/07/2025 09:15, Jay Liu wrote:
> > Add disp-tdshp hardware description for MediaTek MT8196 SoC
> > 
> > Signed-off-by: Jay Liu <jay.liu@mediatek.com>
> > Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
> 
> 
> Who is this person?
> 
> Test your bindings BEFORE you send them, not after. That's v2 so I
> don't
> get why this is not tested at this point.
> 
> 
> Best regards,
> Krzysztof

I apologize for this issue. In the next release, I’ll conduct more
thorough checks to ensure that similar basic mistakes don’t happen
again.

Re: [PATCH v2 1/7] drm/mediatek: Add CCORR component support for MT8196

[AngeloGioacchino Del Regno]

Il 27/07/25 09:15, Jay Liu ha scritto:
> Add CCORR component support for MT8196.
> 
> CCORR is a hardware module that optimizes the visual effects of
> images by adjusting the color matrix, enabling features such as
> night light.
> 
> The 8196 SoC has two CCORR hardware units, which must be chained
> together in a fixed order in the display path to display the image
> correctly. the `mtk_ccorr_ctm_set` API only utilizes one of these units.
> To prevent the unused CCORR unit from inadvertently taking effect,
> we need to block it in the mtk_crtc.c.
> 
> Signed-off-by: Jay Liu <jay.liu@mediatek.com>
> Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>

Please, remove that bogus "20220315152503 created" user that does not exist.

After which:

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH v2 1/7] drm/mediatek: Add CCORR component support for MT8196

[CK Hu (胡俊光)]

On Sun, 2025-07-27 at 15:15 +0800, Jay Liu wrote:
> Add CCORR component support for MT8196.

This patch looks good to me, but I would like the title to be 

drm/mediatek: Support multiple CCORR component

This title is more general not only for MT8196.
In commit message you could keep the MT8196 information because this patch is triggered by MT8196.

Regards,
CK

> 
> CCORR is a hardware module that optimizes the visual effects of
> images by adjusting the color matrix, enabling features such as
> night light.
> 
> The 8196 SoC has two CCORR hardware units, which must be chained
> together in a fixed order in the display path to display the image
> correctly. the `mtk_ccorr_ctm_set` API only utilizes one of these units.
> To prevent the unused CCORR unit from inadvertently taking effect,
> we need to block it in the mtk_crtc.c.
> 
> Signed-off-by: Jay Liu <jay.liu@mediatek.com>
> Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_crtc.c       | 5 ++++-
>  drivers/gpu/drm/mediatek/mtk_ddp_comp.c   | 3 ++-
>  drivers/gpu/drm/mediatek/mtk_ddp_comp.h   | 7 ++++---
>  drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 ++++--
>  drivers/gpu/drm/mediatek/mtk_disp_drv.h   | 2 +-
>  5 files changed, 15 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek/mtk_crtc.c
> index bc7527542fdc..6b9cb52e9207 100644
> --- a/drivers/gpu/drm/mediatek/mtk_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c
> @@ -859,11 +859,14 @@ static void mtk_crtc_atomic_flush(struct drm_crtc *crtc,
>  {
>  	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
>  	int i;
> +	bool ctm_set = false;
>  
>  	if (crtc->state->color_mgmt_changed)
>  		for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
>  			mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> -			mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
> +			/* only set ctm once for the pipeline with two CCORR components */
> +			if (!ctm_set)
> +				ctm_set = mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
>  		}
>  	mtk_crtc_update_config(mtk_crtc, !!mtk_crtc->event);
>  }
> diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> index ac6620e10262..850e3b18da61 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> @@ -458,7 +458,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
>  	[DDP_COMPONENT_AAL0]		= { MTK_DISP_AAL,		0, &ddp_aal },
>  	[DDP_COMPONENT_AAL1]		= { MTK_DISP_AAL,		1, &ddp_aal },
>  	[DDP_COMPONENT_BLS]		= { MTK_DISP_BLS,		0, NULL },
> -	[DDP_COMPONENT_CCORR]		= { MTK_DISP_CCORR,		0, &ddp_ccorr },
> +	[DDP_COMPONENT_CCORR0]		= { MTK_DISP_CCORR,		0, &ddp_ccorr },
> +	[DDP_COMPONENT_CCORR1]		= { MTK_DISP_CCORR,		1, &ddp_ccorr },
>  	[DDP_COMPONENT_COLOR0]		= { MTK_DISP_COLOR,		0, &ddp_color },
>  	[DDP_COMPONENT_COLOR1]		= { MTK_DISP_COLOR,		1, &ddp_color },
>  	[DDP_COMPONENT_DITHER0]		= { MTK_DISP_DITHER,		0, &ddp_dither },
> diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> index 7289b3dcf22f..98a701ac4cde 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> @@ -77,7 +77,7 @@ struct mtk_ddp_comp_funcs {
>  			  struct drm_crtc_state *state);
>  	void (*bgclr_in_on)(struct device *dev);
>  	void (*bgclr_in_off)(struct device *dev);
> -	void (*ctm_set)(struct device *dev,
> +	bool (*ctm_set)(struct device *dev,
>  			struct drm_crtc_state *state);
>  	struct device * (*dma_dev_get)(struct device *dev);
>  	u32 (*get_blend_modes)(struct device *dev);
> @@ -254,11 +254,12 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
>  		comp->funcs->bgclr_in_off(comp->dev);
>  }
>  
> -static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
> +static inline bool mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
>  				   struct drm_crtc_state *state)
>  {
>  	if (comp->funcs && comp->funcs->ctm_set)
> -		comp->funcs->ctm_set(comp->dev, state);
> +		return comp->funcs->ctm_set(comp->dev, state);
> +	return false;
>  }
>  
>  static inline struct device *mtk_ddp_comp_dma_dev_get(struct mtk_ddp_comp *comp)
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> index 10d60d2c2a56..85ba109d6383 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> @@ -101,7 +101,7 @@ static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n)
>  	return r;
>  }
>  
> -void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
> +bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
>  {
>  	struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
>  	struct drm_property_blob *blob = state->ctm;
> @@ -113,7 +113,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
>  	u32 matrix_bits = ccorr->data->matrix_bits;
>  
>  	if (!blob)
> -		return;
> +		return false;
>  
>  	ctm = (struct drm_color_ctm *)blob->data;
>  	input = ctm->matrix;
> @@ -131,6 +131,8 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
>  		      &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3);
>  	mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
>  		      &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4);
> +
> +	return true;
>  }
>  
>  static int mtk_disp_ccorr_bind(struct device *dev, struct device *master,
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 679d413bf10b..4203c28c38ce 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -22,7 +22,7 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state);
>  void mtk_aal_start(struct device *dev);
>  void mtk_aal_stop(struct device *dev);
>  
> -void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state);
> +bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state);
>  int mtk_ccorr_clk_enable(struct device *dev);
>  void mtk_ccorr_clk_disable(struct device *dev);
>  void mtk_ccorr_config(struct device *dev, unsigned int w,

Re: [PATCH v2 2/7] drm/mediatek: fix CCORR mtk_ctm_s31_32_to_s1_n function issue

[CK Hu (胡俊光)]

On Sun, 2025-07-27 at 15:15 +0800, Jay Liu wrote:
> if matrixbit is 11,
> The range of color matrix is from 0 to (BIT(12) - 1).
> Values from 0 to (BIT(11) - 1) represent positive numbers,
> values from BIT(11) to (BIT(12) - 1) represent negative numbers.
> For example, -1 need converted to 8191.
> so convert S31.32 to HW Q2.11 format by drm_color_ctm_s31_32_to_qm_n,
> and set int_bits to 2.

You change the behavior of MT8183 CCORR and MT8192 CCORR.
These two SoC has work for a long time.
Does both SoC really have bug?

In comment below, it shows that HW S1.n format.
The patch sender has much information about the hardware information.
Would they make mistake?
If only MT8196 CCORR has the format qm_n, use private data to distinguish the behavior.

Regards,
CK

> 
> Fixes: 738ed4156fba ("drm/mediatek: Add matrix_bits private data for ccorr")
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: Jay Liu <jay.liu@mediatek.com>
> Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 24 ++---------------------
>  1 file changed, 2 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> index 85ba109d6383..b097c20877f3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> @@ -80,27 +80,6 @@ void mtk_ccorr_stop(struct device *dev)
>  	writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
>  }
>  
> -/* Converts a DRM S31.32 value to the HW S1.n format. */
> -static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n)
> -{
> -	u16 r;
> -
> -	/* Sign bit. */
> -	r = in & BIT_ULL(63) ? BIT(n + 1) : 0;
> -
> -	if ((in & GENMASK_ULL(62, 33)) > 0) {
> -		/* identity value 0x100000000 -> 0x400(mt8183), */
> -		/* identity value 0x100000000 -> 0x800(mt8192), */
> -		/* if bigger this, set it to max 0x7ff. */
> -		r |= GENMASK(n, 0);
> -	} else {
> -		/* take the n+1 most important bits. */
> -		r |= (in >> (32 - n)) & GENMASK(n, 0);
> -	}
> -
> -	return r;
> -}
> -
>  bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
>  {
>  	struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
> @@ -109,6 +88,7 @@ bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
>  	const u64 *input;
>  	uint16_t coeffs[9] = { 0 };
>  	int i;
> +	int int_bits = 2;
>  	struct cmdq_pkt *cmdq_pkt = NULL;
>  	u32 matrix_bits = ccorr->data->matrix_bits;
>  
> @@ -119,7 +99,7 @@ bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
>  	input = ctm->matrix;
>  
>  	for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> -		coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits);
> +		coeffs[i] = drm_color_ctm_s31_32_to_qm_n(input[i], int_bits, matrix_bits);
>  
>  	mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
>  		      &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0);

Re: [PATCH v2 3/7] drm/mediatek: Add TDSHP component support for MT8196

[CK Hu (胡俊光)]

On Sun, 2025-07-27 at 15:15 +0800, Jay Liu wrote:
> Add TDSHP component support for MT8196.
> TDSHP is a hardware module designed to enhance the sharpness and
> clarity of displayed images by analyzing and improving edges and
> fine details in frames.
> 
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: Jay Liu <jay.liu@mediatek.com>
> Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>

After remove 20220315152503,

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> ---
>  drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 49 +++++++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  1 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  2 +
>  3 files changed, 52 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> index 850e3b18da61..c63a12c41215 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> @@ -57,6 +57,14 @@
>  #define POSTMASK_RELAY_MODE				BIT(0)
>  #define DISP_REG_POSTMASK_SIZE			0x0030
>  
> +#define DISP_REG_TDSHP_CTRL			0x0100
> +#define DISP_TDSHP_CTRL_EN			BIT(0)
> +#define DISP_REG_TDSHP_CFG			0x0110
> +#define DISP_TDSHP_RELAY_MODE			BIT(0)
> +#define DISP_REG_TDSHP_INPUT_SIZE		0x0120
> +#define DISP_REG_TDSHP_OUTPUT_OFFSET		0x0124
> +#define DISP_REG_TDSHP_OUTPUT_SIZE		0x0128
> +
>  #define DISP_REG_UFO_START			0x0000
>  #define UFO_BYPASS				BIT(2)
>  
> @@ -261,6 +269,37 @@ static void mtk_postmask_stop(struct device *dev)
>  	writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
>  }
>  
> +static void mtk_disp_tdshp_config(struct device *dev, unsigned int w,
> +				  unsigned int h, unsigned int vrefresh,
> +				  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> +	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
> +		      DISP_REG_TDSHP_INPUT_SIZE);
> +	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
> +		      DISP_REG_TDSHP_OUTPUT_SIZE);
> +	mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs,
> +		      DISP_REG_TDSHP_OUTPUT_OFFSET);
> +
> +	mtk_ddp_write(cmdq_pkt, DISP_TDSHP_RELAY_MODE, &priv->cmdq_reg,
> +		      priv->regs, DISP_REG_TDSHP_CFG);
> +}
> +
> +static void mtk_disp_tdshp_start(struct device *dev)
> +{
> +	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +	writel(DISP_TDSHP_CTRL_EN, priv->regs + DISP_REG_TDSHP_CTRL);
> +}
> +
> +static void mtk_disp_tdshp_stop(struct device *dev)
> +{
> +	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +	writel(0, priv->regs + DISP_REG_TDSHP_CTRL);
> +}
> +
>  static void mtk_ufoe_start(struct device *dev)
>  {
>  	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> @@ -268,6 +307,14 @@ static void mtk_ufoe_start(struct device *dev)
>  	writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
>  }
>  
> +static const struct mtk_ddp_comp_funcs ddp_tdshp = {
> +	.clk_enable = mtk_ddp_clk_enable,
> +	.clk_disable = mtk_ddp_clk_disable,
> +	.config = mtk_disp_tdshp_config,
> +	.start = mtk_disp_tdshp_start,
> +	.stop = mtk_disp_tdshp_stop,
> +};
> +
>  static const struct mtk_ddp_comp_funcs ddp_aal = {
>  	.clk_enable = mtk_aal_clk_enable,
>  	.clk_disable = mtk_aal_clk_disable,
> @@ -441,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
>  	[MTK_DISP_POSTMASK] = "postmask",
>  	[MTK_DISP_PWM] = "pwm",
>  	[MTK_DISP_RDMA] = "rdma",
> +	[MTK_DISP_TDSHP] = "tdshp",
>  	[MTK_DISP_UFOE] = "ufoe",
>  	[MTK_DISP_WDMA] = "wdma",
>  	[MTK_DP_INTF] = "dp-intf",
> @@ -496,6 +544,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
>  	[DDP_COMPONENT_RDMA1]		= { MTK_DISP_RDMA,		1, &ddp_rdma },
>  	[DDP_COMPONENT_RDMA2]		= { MTK_DISP_RDMA,		2, &ddp_rdma },
>  	[DDP_COMPONENT_RDMA4]		= { MTK_DISP_RDMA,		4, &ddp_rdma },
> +	[DDP_COMPONENT_TDSHP0]		= { MTK_DISP_TDSHP,		0, &ddp_tdshp },
>  	[DDP_COMPONENT_UFOE]		= { MTK_DISP_UFOE,		0, &ddp_ufoe },
>  	[DDP_COMPONENT_WDMA0]		= { MTK_DISP_WDMA,		0, NULL },
>  	[DDP_COMPONENT_WDMA1]		= { MTK_DISP_WDMA,		1, NULL },
> diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> index 98a701ac4cde..a03fa3385d2f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> @@ -38,6 +38,7 @@ enum mtk_ddp_comp_type {
>  	MTK_DISP_POSTMASK,
>  	MTK_DISP_PWM,
>  	MTK_DISP_RDMA,
> +	MTK_DISP_TDSHP,
>  	MTK_DISP_UFOE,
>  	MTK_DISP_WDMA,
>  	MTK_DPI,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index d5e6bab36414..042cf03c7a54 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -812,6 +812,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>  	  .data = (void *)MTK_DISP_RDMA },
>  	{ .compatible = "mediatek,mt8195-disp-rdma",
>  	  .data = (void *)MTK_DISP_RDMA },
> +	{ .compatible = "mediatek,mt8196-disp-tdshp",
> +	  .data = (void *)MTK_DISP_TDSHP },
>  	{ .compatible = "mediatek,mt8173-disp-ufoe",
>  	  .data = (void *)MTK_DISP_UFOE },
>  	{ .compatible = "mediatek,mt8173-disp-wdma",

Re: [PATCH v2 4/7] dt-bindings: display: mediatek: disp-tdshp: Add support for MT8196

[CK Hu (胡俊光)]

On Sun, 2025-07-27 at 15:15 +0800, Jay Liu wrote:
> Add disp-tdshp hardware description for MediaTek MT8196 SoC
> 
> Signed-off-by: Jay Liu <jay.liu@mediatek.com>
> Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
> ---
>  .../display/mediatek/mediatek,disp-tdshp.yaml | 50 +++++++++++++++++++
>  1 file changed, 50 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml
> new file mode 100644
> index 000000000000..3d95ecfc0d19
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml
> @@ -0,0 +1,50 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,disp-tdshp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek display 2D sharpness processor
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  MediaTek display 2D sharpness processor, namely TDSHP, provides a
> +  operation used to adjust sharpness in display system.
> +  TDSHP device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +      - enum:
> +          - mediatek,mt8196-disp-tdshp

Patch [3/7] tdshp driver depend on this compatible string, so patch [3/7] depend on patch [4/7].
The patch order is weird.
Usually the binding document is in front of a series then follow the driver.

Regards,
CK

> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        disp-tdshp@321e0000 {
> +            compatible = "mediatek,mt8196-disp-tdshp";
> +            reg = <0 0x321e0000 0 0x1000>;
> +            clocks = <&dispsys_config_clk 107>;
> +        };
> +    };

Re: [PATCH v2 6/7] dt-bindings: display: mediatek: dither: Add support for MT8196

[CK Hu (胡俊光)]

On Sun, 2025-07-27 at 15:15 +0800, Jay Liu wrote:
> Add a compatible string for the DITHER IP found in the MT8196 SoC.
> Each DITHER IP of this SoC is fully compatible with the ones found
> in MT8183.
> 
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: Jay Liu <jay.liu@mediatek.com>
> Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
> ---
>  .../devicetree/bindings/display/mediatek/mediatek,dither.yaml    | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> index abaf27916d13..1f1719228b5d 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> @@ -31,6 +31,7 @@ properties:
>                - mediatek,mt8192-disp-dither
>                - mediatek,mt8195-disp-dither
>                - mediatek,mt8365-disp-dither
> +              - mediatek,mt8196-disp-dither

Let the number from small to large in order.

Regards,
CK

>            - const: mediatek,mt8183-disp-dither
>  
>    reg:

Re: [PATCH v2 2/7] drm/mediatek: fix CCORR mtk_ctm_s31_32_to_s1_n function issue

[Jay Liu (刘博)]

On Wed, 2025-08-06 at 06:37 +0000, CK Hu (胡俊光) wrote:
> On Sun, 2025-07-27 at 15:15 +0800, Jay Liu wrote:
> > if matrixbit is 11,
> > The range of color matrix is from 0 to (BIT(12) - 1).
> > Values from 0 to (BIT(11) - 1) represent positive numbers,
> > values from BIT(11) to (BIT(12) - 1) represent negative numbers.
> > For example, -1 need converted to 8191.
> > so convert S31.32 to HW Q2.11 format by
> > drm_color_ctm_s31_32_to_qm_n,
> > and set int_bits to 2.
> 
> You change the behavior of MT8183 CCORR and MT8192 CCORR.
> These two SoC has work for a long time.
> Does both SoC really have bug?
> 
> In comment below, it shows that HW S1.n format.
> The patch sender has much information about the hardware information.
> Would they make mistake?
> If only MT8196 CCORR has the format qm_n, use private data to
> distinguish the behavior.
> 
> Regards,
> CK
> 
Yes. We received an email from customer, they found that the previous
patch failed to handle negative values correctly, so the result was not
as expected and they would like this issue fixed in the current update.
We also consulted with the DE; the hardware itself supports negative
numbers and all ICs behave the same in this regard. The current patch
converts negative values into a format that the hardware can properly
recognize.

Best Regards,
Jay Liu

> > 
> > Fixes: 738ed4156fba ("drm/mediatek: Add matrix_bits private data
> > for ccorr")
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > Signed-off-by: Jay Liu <jay.liu@mediatek.com>
> > Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 24 ++-----------------
> > ----
> >  1 file changed, 2 insertions(+), 22 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> > index 85ba109d6383..b097c20877f3 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> > @@ -80,27 +80,6 @@ void mtk_ccorr_stop(struct device *dev)
> >  	writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
> >  }
> >  
> > -/* Converts a DRM S31.32 value to the HW S1.n format. */
> > -static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n)
> > -{
> > -	u16 r;
> > -
> > -	/* Sign bit. */
> > -	r = in & BIT_ULL(63) ? BIT(n + 1) : 0;
> > -
> > -	if ((in & GENMASK_ULL(62, 33)) > 0) {
> > -		/* identity value 0x100000000 -> 0x400(mt8183), */
> > -		/* identity value 0x100000000 -> 0x800(mt8192), */
> > -		/* if bigger this, set it to max 0x7ff. */
> > -		r |= GENMASK(n, 0);
> > -	} else {
> > -		/* take the n+1 most important bits. */
> > -		r |= (in >> (32 - n)) & GENMASK(n, 0);
> > -	}
> > -
> > -	return r;
> > -}
> > -
> >  bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state
> > *state)
> >  {
> >  	struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
> > @@ -109,6 +88,7 @@ bool mtk_ccorr_ctm_set(struct device *dev,
> > struct drm_crtc_state *state)
> >  	const u64 *input;
> >  	uint16_t coeffs[9] = { 0 };
> >  	int i;
> > +	int int_bits = 2;
> >  	struct cmdq_pkt *cmdq_pkt = NULL;
> >  	u32 matrix_bits = ccorr->data->matrix_bits;
> >  
> > @@ -119,7 +99,7 @@ bool mtk_ccorr_ctm_set(struct device *dev,
> > struct drm_crtc_state *state)
> >  	input = ctm->matrix;
> >  
> >  	for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> > -		coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i],
> > matrix_bits);
> > +		coeffs[i] = drm_color_ctm_s31_32_to_qm_n(input[i],
> > int_bits, matrix_bits);
> >  
> >  	mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> >  		      &ccorr->cmdq_reg, ccorr->regs,
> > DISP_CCORR_COEF_0);
> 
> 

Re: [PATCH v2 2/7] drm/mediatek: fix CCORR mtk_ctm_s31_32_to_s1_n function issue

[CK Hu (胡俊光)]

On Thu, 2025-08-07 at 06:19 +0000, Jay Liu (刘博) wrote:
> On Wed, 2025-08-06 at 06:37 +0000, CK Hu (胡俊光) wrote:
> > On Sun, 2025-07-27 at 15:15 +0800, Jay Liu wrote:
> > > if matrixbit is 11,
> > > The range of color matrix is from 0 to (BIT(12) - 1).
> > > Values from 0 to (BIT(11) - 1) represent positive numbers,
> > > values from BIT(11) to (BIT(12) - 1) represent negative numbers.
> > > For example, -1 need converted to 8191.
> > > so convert S31.32 to HW Q2.11 format by
> > > drm_color_ctm_s31_32_to_qm_n,
> > > and set int_bits to 2.
> > 
> > You change the behavior of MT8183 CCORR and MT8192 CCORR.
> > These two SoC has work for a long time.
> > Does both SoC really have bug?
> > 
> > In comment below, it shows that HW S1.n format.
> > The patch sender has much information about the hardware information.
> > Would they make mistake?
> > If only MT8196 CCORR has the format qm_n, use private data to
> > distinguish the behavior.
> > 
> > Regards,
> > CK
> > 
> Yes. We received an email from customer, they found that the previous
> patch failed to handle negative values correctly, so the result was not
> as expected and they would like this issue fixed in the current update.
> We also consulted with the DE; the hardware itself supports negative
> numbers and all ICs behave the same in this regard. The current patch
> converts negative values into a format that the hardware can properly
> recognize.

OK, move this patch out of this series.
Send this patch independently.
And this is a fixup patch, so Add 'Fixes' tag.

Regards,
CK

> 
> Best Regards,
> Jay Liu
> 
> > > 
> > > Fixes: 738ed4156fba ("drm/mediatek: Add matrix_bits private data
> > > for ccorr")
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > Signed-off-by: Jay Liu <jay.liu@mediatek.com>
> > > Signed-off-by: 20220315152503 created <jay.liu@mediatek.com>
> > > ---
> > >  drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 24 ++-----------------
> > > ----
> > >  1 file changed, 2 insertions(+), 22 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> > > b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> > > index 85ba109d6383..b097c20877f3 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> > > @@ -80,27 +80,6 @@ void mtk_ccorr_stop(struct device *dev)
> > >  	writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
> > >  }
> > >  
> > > -/* Converts a DRM S31.32 value to the HW S1.n format. */
> > > -static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n)
> > > -{
> > > -	u16 r;
> > > -
> > > -	/* Sign bit. */
> > > -	r = in & BIT_ULL(63) ? BIT(n + 1) : 0;
> > > -
> > > -	if ((in & GENMASK_ULL(62, 33)) > 0) {
> > > -		/* identity value 0x100000000 -> 0x400(mt8183), */
> > > -		/* identity value 0x100000000 -> 0x800(mt8192), */
> > > -		/* if bigger this, set it to max 0x7ff. */
> > > -		r |= GENMASK(n, 0);
> > > -	} else {
> > > -		/* take the n+1 most important bits. */
> > > -		r |= (in >> (32 - n)) & GENMASK(n, 0);
> > > -	}
> > > -
> > > -	return r;
> > > -}
> > > -
> > >  bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state
> > > *state)
> > >  {
> > >  	struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
> > > @@ -109,6 +88,7 @@ bool mtk_ccorr_ctm_set(struct device *dev,
> > > struct drm_crtc_state *state)
> > >  	const u64 *input;
> > >  	uint16_t coeffs[9] = { 0 };
> > >  	int i;
> > > +	int int_bits = 2;
> > >  	struct cmdq_pkt *cmdq_pkt = NULL;
> > >  	u32 matrix_bits = ccorr->data->matrix_bits;
> > >  
> > > @@ -119,7 +99,7 @@ bool mtk_ccorr_ctm_set(struct device *dev,
> > > struct drm_crtc_state *state)
> > >  	input = ctm->matrix;
> > >  
> > >  	for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> > > -		coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i],
> > > matrix_bits);
> > > +		coeffs[i] = drm_color_ctm_s31_32_to_qm_n(input[i],
> > > int_bits, matrix_bits);
> > >  
> > >  	mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> > >  		      &ccorr->cmdq_reg, ccorr->regs,
> > > DISP_CCORR_COEF_0);
> > 
> >