[PATCH v12 4/7] PCI: keystone: Add support for PVU-based DMA isolation on AM654

huaqian.li
2025-07-28T02:50:22Z

From: Jan Kiszka <jan.kiszka@siemens.com>

The AM654 lacks an IOMMU, thus does not support isolating DMA requests
from untrusted PCI devices to selected memory regions this way. Use
static PVU-based protection instead. The PVU, when enabled, will only
accept DMA requests that address previously configured regions.

Use the availability of a restricted-dma-pool memory region as trigger
and register it as valid DMA target with the PVU. In addition, enable
the mapping of requester IDs to VirtIDs in the PCI RC. Use only a single
VirtID so far, catching all devices.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Li Hua Qian <huaqian.li@siemens.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
drivers/pci/controller/dwc/pci-keystone.c | 118 +++++++++++++++++++++-
1 file changed, 115 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index 2b2632e513b5..c4a0947b8a00 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -19,6 +19,7 @@
#include <linux/mfd/syscon.h>
#include <linux/msi.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/phy/phy.h>
@@ -26,6 +27,7 @@
#include <linux/regmap.h>
#include <linux/resource.h>
#include <linux/signal.h>
+#include <linux/ti-pvu.h>

#include "../../pci.h"
#include "pcie-designware.h"
@@ -111,6 +113,16 @@

#define PCI_DEVICE_ID_TI_AM654X 0xb00c

+#define KS_PCI_VIRTID 0
+
+#define PCIE_VMAP_xP_CTRL 0x0
+#define PCIE_VMAP_xP_REQID 0x4
+#define PCIE_VMAP_xP_VIRTID 0x8
+
+#define PCIE_VMAP_xP_CTRL_EN BIT(0)
+
+#define PCIE_VMAP_xP_VIRTID_VID_MASK 0xfff
+
struct ks_pcie_of_data {
enum dw_pcie_device_mode mode;
const struct dw_pcie_host_ops *host_ops;
@@ -1136,6 +1148,94 @@ static const struct of_device_id ks_pcie_of_match[] = {
{ },
};

+static int ks_init_vmap(struct platform_device *pdev, const char *vmap_name)
+{
+ struct resource *res;
+ void __iomem *base;
+ u32 val;
+
+ if (!IS_ENABLED(CONFIG_TI_PVU))
+ return 0;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, vmap_name);
+ base = devm_pci_remap_cfg_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ writel(0, base + PCIE_VMAP_xP_REQID);
+
+ val = readl(base + PCIE_VMAP_xP_VIRTID);
+ val &= ~PCIE_VMAP_xP_VIRTID_VID_MASK;
+ val |= KS_PCI_VIRTID;
+ writel(val, base + PCIE_VMAP_xP_VIRTID);
+
+ val = readl(base + PCIE_VMAP_xP_CTRL);
+ val |= PCIE_VMAP_xP_CTRL_EN;
+ writel(val, base + PCIE_VMAP_xP_CTRL);
+
+ return 0;
+}
+
+static int ks_init_restricted_dma(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct of_phandle_iterator it;
+ struct resource phys;
+ int err;
+
+ if (!IS_ENABLED(CONFIG_TI_PVU))
+ return 0;
+
+ /* Only process the first restricted DMA pool, more are not allowed */
+ of_for_each_phandle(&it, err, dev->of_node, "memory-region",
+ NULL, 0) {
+ if (of_device_is_compatible(it.node, "restricted-dma-pool"))
+ break;
+ }
+ if (err)
+ return err == -ENOENT ? 0 : err;
+
+ err = of_address_to_resource(it.node, 0, &phys);
+ if (err < 0) {
+ dev_err(dev, "failed to parse memory region %pOF: %d\n",
+ it.node, err);
+ return 0;
+ }
+
+ /* Map all incoming requests on low and high prio port to virtID 0 */
+ err = ks_init_vmap(pdev, "vmap_lp");
+ if (err)
+ return err;
+ err = ks_init_vmap(pdev, "vmap_hp");
+ if (err)
+ return err;
+
+ /*
+ * Enforce DMA pool usage with the help of the PVU.
+ * Any request outside will be dropped and raise an error at the PVU.
+ */
+ return ti_pvu_create_region(KS_PCI_VIRTID, &phys);
+}
+
+static void ks_release_restricted_dma(struct platform_device *pdev)
+{
+ struct of_phandle_iterator it;
+ struct resource phys;
+ int err;
+
+ if (!IS_ENABLED(CONFIG_TI_PVU))
+ return;
+
+ of_for_each_phandle(&it, err, pdev->dev.of_node, "memory-region",
+ NULL, 0) {
+ if (of_device_is_compatible(it.node, "restricted-dma-pool") &&
+ of_address_to_resource(it.node, 0, &phys) == 0) {
+ ti_pvu_remove_region(KS_PCI_VIRTID, &phys);
+ break;
+ }
+ }
+}
+
static int ks_pcie_probe(struct platform_device *pdev)
{
const struct dw_pcie_host_ops *host_ops;
@@ -1286,15 +1386,19 @@ static int ks_pcie_probe(struct platform_device *pdev)

switch (mode) {
case DW_PCIE_RC_TYPE:
+ ret = ks_init_restricted_dma(pdev);
+ if (ret < 0)
+ goto err_get_sync;
+
if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) {
ret = -ENODEV;
- goto err_get_sync;
+ goto err_dma_cleanup;
}

ret = of_property_read_u32(np, "num-viewport", &num_viewport);
if (ret < 0) {
dev_err(dev, "unable to read *num-viewport* property\n");
- goto err_get_sync;
+ goto err_dma_cleanup;
}

/*
@@ -1314,7 +1418,7 @@ static int ks_pcie_probe(struct platform_device *pdev)
pci->pp.ops = host_ops;
ret = dw_pcie_host_init(&pci->pp);
if (ret < 0)
- goto err_get_sync;
+ goto err_dma_cleanup;
break;
case DW_PCIE_EP_TYPE:
if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) {
@@ -1346,6 +1450,9 @@ static int ks_pcie_probe(struct platform_device *pdev)

err_ep_init:
dw_pcie_ep_deinit(&pci->ep);
+err_dma_cleanup:
+ if (mode == DW_PCIE_RC_TYPE)
+ ks_release_restricted_dma(pdev);
err_get_sync:
pm_runtime_put(dev);
pm_runtime_disable(dev);
@@ -1362,9 +1469,14 @@ static void ks_pcie_remove(struct platform_device *pdev)
{
struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
struct device_link **link = ks_pcie->link;
+ const struct ks_pcie_of_data *data;
int num_lanes = ks_pcie->num_lanes;
struct device *dev = &pdev->dev;

+ data = of_device_get_match_data(dev);
+ if (data && data->mode == DW_PCIE_RC_TYPE)
+ ks_release_restricted_dma(pdev);
+
pm_runtime_put(dev);
pm_runtime_disable(dev);
ks_pcie_disable_phy(ks_pcie);
--
2.34.1