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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4589ee57c18sm28121285e9.28.2025.07.31.07.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Jul 2025 07:01:55 -0700 (PDT) From: Daniel Lezcano To: mbrugger@suse.com, chester62515@gmail.com, ghennadi.procopciuc@oss.nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: s32@nxp.com, kernel@pengutronix.de, festevam@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/8] Add the STM and the SWT nodes for the s32g2 and s32g3 Date: Thu, 31 Jul 2025 16:01:33 +0200 Message-ID: <20250731140146.62960-1-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250731_070158_690933_B05241E5 X-CRM114-Status: GOOD ( 13.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The NXP S32 SoC family includes timers and watchdogs that can be dedicated to the CPUs present in the system. The documentation refers to them as the System Timer Module (STM) and the Software Watchdog Timer (SWT). This design originates from the automotive domain, where the SoC can be partitioned, and a group of CPUs may run different operating systems or firmware. On the S32G2, we found 8 timers and 7 watchdogs. On the S32G3, there are 12 timers and 12 watchdogs. Please note that the 8th timer (STM_07) is not described here, as it is coupled with a specific STM instance used for timestamping. This makes it somewhat special and requires custom handling in the driver. It will be added later. All timers and watchdogs are disabled by default, and are selectively enabled depending on the platform configuration, which may include different combinations of Cortex-M7 and Cortex-A53 cores. This patch series introduces support for the SoC and enables both the s32g274a-rdb2 and s32g399a-rdb3 platforms. Testing was done only on the s32g274a-rdb2, as I do not have access to a s32g399a-rdb3 board. Changelog: v2: - Replace the 'description' word usage by 'node - Reordered the nodes in DT regarding the address ranges - Modified the change description to leave the ambiguity regarding the architected timers Daniel Lezcano (8): arm64: dts: s32g2: Add the System Timer Module nodes arm64: dts: s32g274-rd2: Enable the STM timers arm64: dts: s32g3: Add the System Timer Module nodes arm64: dts: s32g399a-rdb3: Enable the STM timers arm64: dts: s32g2: Add the Software Timer Watchdog (SWT) nodes arm64: dts: s32g274-rd2: Enable the SWT watchdog arm64: dts: s32g3: Add the Software Timer Watchdog (SWT) nodes arm64: dts: s32g399a-rdb3: Enable the SWT watchdog arch/arm64/boot/dts/freescale/s32g2.dtsi | 119 +++++++++++ .../boot/dts/freescale/s32g274a-rdb2.dts | 20 ++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 195 ++++++++++++++++++ .../boot/dts/freescale/s32g399a-rdb3.dts | 36 ++++ 4 files changed, 370 insertions(+) -- 2.43.0