* [PATCH v2 0/2] Add support for AM62P SR1.2 @ 2025-08-07 22:51 Judith Mendez 2025-08-07 22:51 ` [PATCH v2 1/2] soc: ti: k3-socinfo: Add support for AM62P variants Judith Mendez 2025-08-07 22:51 ` [PATCH v2 2/2] mmc: sdhci_am654: Disable HS400 for AM62P SR1.0 and SR1.1 Judith Mendez 0 siblings, 2 replies; 6+ messages in thread From: Judith Mendez @ 2025-08-07 22:51 UTC (permalink / raw) To: Judith Mendez, Adrian Hunter, Ulf Hansson, Nishanth Menon, Santosh Shilimkar Cc: linux-mmc, linux-kernel, linux-arm-kernel, Andrew Davis This patch series adds support for the AM62P SR1.2 silicon revision by adding logic in k3-socinfo to detect AM62P variants. This also disables HS400 support for AM62P SR1.0 and SR1.1 in sdhci host driver and enable by default for AM62P SR1.2. Tested against AM62P SR1.2, SR1.1, SR1.0 and AM62X SK. Log for AM62P SR1.2: https://gist.github.com/jmenti/3d605dcd9445c2fac86c626bfa519103 Changes since v1: - Drop binding and DT patches - Move disable HS400 print to sdhci_am654_init & only print if caps are already enabled, according to Andrew's review - Completely refactor/change patch 2/4 for k3-socinfo to not add a new item to reg property, find GP_SW as an offset of JTAG ID. This approach is based off-of Krzysztof's review. Link to v1: https://lore.kernel.org/linux-mmc/20250805234950.3781367-1-jm@ti.com Judith Mendez (2): soc: ti: k3-socinfo: Add support for AM62P variants mmc: sdhci_am654: Disable HS400 for AM62P SR1.0 and SR1.1 drivers/mmc/host/sdhci_am654.c | 18 ++++++++++++++++++ drivers/soc/ti/k3-socinfo.c | 27 +++++++++++++++++++++++++-- 2 files changed, 43 insertions(+), 2 deletions(-) -- 2.49.0 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/2] soc: ti: k3-socinfo: Add support for AM62P variants 2025-08-07 22:51 [PATCH v2 0/2] Add support for AM62P SR1.2 Judith Mendez @ 2025-08-07 22:51 ` Judith Mendez 2025-08-08 13:50 ` Andrew Davis 2025-08-07 22:51 ` [PATCH v2 2/2] mmc: sdhci_am654: Disable HS400 for AM62P SR1.0 and SR1.1 Judith Mendez 1 sibling, 1 reply; 6+ messages in thread From: Judith Mendez @ 2025-08-07 22:51 UTC (permalink / raw) To: Judith Mendez, Adrian Hunter, Ulf Hansson, Nishanth Menon, Santosh Shilimkar Cc: linux-mmc, linux-kernel, linux-arm-kernel, Andrew Davis This adds a support for detecting AM62P SR1.0, SR1.1, SR1.2. On AM62P, silicon revision is discovered with GP_SW1 instead of JTAGID register, so read GP_SW1 to determine SoC revision only on AM62P. Signed-off-by: Judith Mendez <jm@ti.com> --- drivers/soc/ti/k3-socinfo.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c index d716be113c84..81d078f15cd2 100644 --- a/drivers/soc/ti/k3-socinfo.c +++ b/drivers/soc/ti/k3-socinfo.c @@ -15,6 +15,9 @@ #include <linux/sys_soc.h> #define CTRLMMR_WKUP_JTAGID_REG 0 +#define CTRLMMR_WKUP_GP_SW1_OFFSET 544 +#define GP_SW1_MOD_OPR 16 + /* * Bits: * 31-28 VARIANT Device variant @@ -66,6 +69,10 @@ static const char * const j721e_rev_string_map[] = { "1.0", "1.1", "2.0", }; +static const char * const am62p_gpsw_rev_string_map[] = { + "1.0", "1.1", "1.2", +}; + static int k3_chipinfo_partno_to_names(unsigned int partno, struct soc_device_attribute *soc_dev_attr) @@ -83,7 +90,7 @@ k3_chipinfo_partno_to_names(unsigned int partno, static int k3_chipinfo_variant_to_sr(unsigned int partno, unsigned int variant, - struct soc_device_attribute *soc_dev_attr) + struct soc_device_attribute *soc_dev_attr, u32 gp_sw1) { switch (partno) { case JTAG_ID_PARTNO_J721E: @@ -92,6 +99,14 @@ k3_chipinfo_variant_to_sr(unsigned int partno, unsigned int variant, soc_dev_attr->revision = kasprintf(GFP_KERNEL, "SR%s", j721e_rev_string_map[variant]); break; + case JTAG_ID_PARTNO_AM62PX: + /* Always parse AM62P variant from GP_SW1 */ + variant = gp_sw1 % GP_SW1_MOD_OPR; + if (variant >= ARRAY_SIZE(am62p_gpsw_rev_string_map)) + goto err_unknown_variant; + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "SR%s", + am62p_gpsw_rev_string_map[variant]); + break; default: variant++; soc_dev_attr->revision = kasprintf(GFP_KERNEL, "SR%x.0", @@ -121,6 +136,7 @@ static int k3_chipinfo_probe(struct platform_device *pdev) struct soc_device *soc_dev; struct regmap *regmap; void __iomem *base; + u32 gp_sw1_val = 0; u32 partno_id; u32 variant; u32 jtag_id; @@ -163,7 +179,14 @@ static int k3_chipinfo_probe(struct platform_device *pdev) goto err; } - ret = k3_chipinfo_variant_to_sr(partno_id, variant, soc_dev_attr); + if (partno_id == JTAG_ID_PARTNO_AM62PX) { + ret = regmap_read(regmap, CTRLMMR_WKUP_JTAGID_REG + + CTRLMMR_WKUP_GP_SW1_OFFSET, &gp_sw1_val); + if (ret < 0) + goto err; + } + + ret = k3_chipinfo_variant_to_sr(partno_id, variant, soc_dev_attr, gp_sw1_val); if (ret) { dev_err(dev, "Unknown SoC SR[0x%08X]: %d\n", jtag_id, ret); goto err; -- 2.49.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] soc: ti: k3-socinfo: Add support for AM62P variants 2025-08-07 22:51 ` [PATCH v2 1/2] soc: ti: k3-socinfo: Add support for AM62P variants Judith Mendez @ 2025-08-08 13:50 ` Andrew Davis 2025-08-08 14:51 ` Judith Mendez 0 siblings, 1 reply; 6+ messages in thread From: Andrew Davis @ 2025-08-08 13:50 UTC (permalink / raw) To: Judith Mendez, Adrian Hunter, Ulf Hansson, Nishanth Menon, Santosh Shilimkar Cc: linux-mmc, linux-kernel, linux-arm-kernel On 8/7/25 5:51 PM, Judith Mendez wrote: > This adds a support for detecting AM62P SR1.0, SR1.1, SR1.2. > > On AM62P, silicon revision is discovered with GP_SW1 instead of JTAGID > register, so read GP_SW1 to determine SoC revision only on AM62P. > > Signed-off-by: Judith Mendez <jm@ti.com> > --- > drivers/soc/ti/k3-socinfo.c | 27 +++++++++++++++++++++++++-- > 1 file changed, 25 insertions(+), 2 deletions(-) > > diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c > index d716be113c84..81d078f15cd2 100644 > --- a/drivers/soc/ti/k3-socinfo.c > +++ b/drivers/soc/ti/k3-socinfo.c > @@ -15,6 +15,9 @@ > #include <linux/sys_soc.h> > > #define CTRLMMR_WKUP_JTAGID_REG 0 > +#define CTRLMMR_WKUP_GP_SW1_OFFSET 544 > +#define GP_SW1_MOD_OPR 16 > + > /* > * Bits: > * 31-28 VARIANT Device variant > @@ -66,6 +69,10 @@ static const char * const j721e_rev_string_map[] = { > "1.0", "1.1", "2.0", > }; > > +static const char * const am62p_gpsw_rev_string_map[] = { > + "1.0", "1.1", "1.2", > +}; > + > static int > k3_chipinfo_partno_to_names(unsigned int partno, > struct soc_device_attribute *soc_dev_attr) > @@ -83,7 +90,7 @@ k3_chipinfo_partno_to_names(unsigned int partno, > > static int > k3_chipinfo_variant_to_sr(unsigned int partno, unsigned int variant, > - struct soc_device_attribute *soc_dev_attr) > + struct soc_device_attribute *soc_dev_attr, u32 gp_sw1) > { > switch (partno) { > case JTAG_ID_PARTNO_J721E: > @@ -92,6 +99,14 @@ k3_chipinfo_variant_to_sr(unsigned int partno, unsigned int variant, > soc_dev_attr->revision = kasprintf(GFP_KERNEL, "SR%s", > j721e_rev_string_map[variant]); > break; > + case JTAG_ID_PARTNO_AM62PX: > + /* Always parse AM62P variant from GP_SW1 */ > + variant = gp_sw1 % GP_SW1_MOD_OPR; > + if (variant >= ARRAY_SIZE(am62p_gpsw_rev_string_map)) > + goto err_unknown_variant; > + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "SR%s", > + am62p_gpsw_rev_string_map[variant]); > + break; > default: > variant++; > soc_dev_attr->revision = kasprintf(GFP_KERNEL, "SR%x.0", > @@ -121,6 +136,7 @@ static int k3_chipinfo_probe(struct platform_device *pdev) > struct soc_device *soc_dev; > struct regmap *regmap; > void __iomem *base; > + u32 gp_sw1_val = 0; > u32 partno_id; > u32 variant; > u32 jtag_id; > @@ -163,7 +179,14 @@ static int k3_chipinfo_probe(struct platform_device *pdev) > goto err; > } > > - ret = k3_chipinfo_variant_to_sr(partno_id, variant, soc_dev_attr); > + if (partno_id == JTAG_ID_PARTNO_AM62PX) { > + ret = regmap_read(regmap, CTRLMMR_WKUP_JTAGID_REG + > + CTRLMMR_WKUP_GP_SW1_OFFSET, &gp_sw1_val); This is wrong, you cannot read from the register GP_SW1 (offset 544). In DT the region is 4 bytes long (reg = <0x14 0x4>;). This only worked in your testing because the above ioremap_resource() has to map in page sized(4K) chunks and we didn't set max_register in our regmap_config so no bounds checking is done. If we fix either of the above then this read will stop working. So yes you'll have to make DT changes and fight it out with Krzysztof. My suggestion is to make a efuse region for the 3 GPSW registers and use a phandle from this node to fetch the extra info you need to get revision. Andrew > + if (ret < 0) > + goto err; > + } > + > + ret = k3_chipinfo_variant_to_sr(partno_id, variant, soc_dev_attr, gp_sw1_val); > if (ret) { > dev_err(dev, "Unknown SoC SR[0x%08X]: %d\n", jtag_id, ret); > goto err; ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] soc: ti: k3-socinfo: Add support for AM62P variants 2025-08-08 13:50 ` Andrew Davis @ 2025-08-08 14:51 ` Judith Mendez 0 siblings, 0 replies; 6+ messages in thread From: Judith Mendez @ 2025-08-08 14:51 UTC (permalink / raw) To: Andrew Davis, Adrian Hunter, Ulf Hansson, Nishanth Menon, Santosh Shilimkar Cc: linux-mmc, linux-kernel, linux-arm-kernel Hi Andrew, On 8/8/25 8:50 AM, Andrew Davis wrote: > On 8/7/25 5:51 PM, Judith Mendez wrote: >> This adds a support for detecting AM62P SR1.0, SR1.1, SR1.2. >> >> On AM62P, silicon revision is discovered with GP_SW1 instead of JTAGID >> register, so read GP_SW1 to determine SoC revision only on AM62P. >> >> Signed-off-by: Judith Mendez <jm@ti.com> >> --- >> drivers/soc/ti/k3-socinfo.c | 27 +++++++++++++++++++++++++-- >> 1 file changed, 25 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c >> index d716be113c84..81d078f15cd2 100644 >> --- a/drivers/soc/ti/k3-socinfo.c >> +++ b/drivers/soc/ti/k3-socinfo.c >> @@ -15,6 +15,9 @@ >> #include <linux/sys_soc.h> >> #define CTRLMMR_WKUP_JTAGID_REG 0 >> +#define CTRLMMR_WKUP_GP_SW1_OFFSET 544 >> +#define GP_SW1_MOD_OPR 16 >> + >> /* >> * Bits: >> * 31-28 VARIANT Device variant >> @@ -66,6 +69,10 @@ static const char * const j721e_rev_string_map[] = { >> "1.0", "1.1", "2.0", >> }; >> +static const char * const am62p_gpsw_rev_string_map[] = { >> + "1.0", "1.1", "1.2", >> +}; >> + >> static int >> k3_chipinfo_partno_to_names(unsigned int partno, >> struct soc_device_attribute *soc_dev_attr) >> @@ -83,7 +90,7 @@ k3_chipinfo_partno_to_names(unsigned int partno, >> static int >> k3_chipinfo_variant_to_sr(unsigned int partno, unsigned int variant, >> - struct soc_device_attribute *soc_dev_attr) >> + struct soc_device_attribute *soc_dev_attr, u32 gp_sw1) >> { >> switch (partno) { >> case JTAG_ID_PARTNO_J721E: >> @@ -92,6 +99,14 @@ k3_chipinfo_variant_to_sr(unsigned int partno, >> unsigned int variant, >> soc_dev_attr->revision = kasprintf(GFP_KERNEL, "SR%s", >> j721e_rev_string_map[variant]); >> break; >> + case JTAG_ID_PARTNO_AM62PX: >> + /* Always parse AM62P variant from GP_SW1 */ >> + variant = gp_sw1 % GP_SW1_MOD_OPR; >> + if (variant >= ARRAY_SIZE(am62p_gpsw_rev_string_map)) >> + goto err_unknown_variant; >> + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "SR%s", >> + am62p_gpsw_rev_string_map[variant]); >> + break; >> default: >> variant++; >> soc_dev_attr->revision = kasprintf(GFP_KERNEL, "SR%x.0", >> @@ -121,6 +136,7 @@ static int k3_chipinfo_probe(struct >> platform_device *pdev) >> struct soc_device *soc_dev; >> struct regmap *regmap; >> void __iomem *base; >> + u32 gp_sw1_val = 0; >> u32 partno_id; >> u32 variant; >> u32 jtag_id; >> @@ -163,7 +179,14 @@ static int k3_chipinfo_probe(struct >> platform_device *pdev) >> goto err; >> } >> - ret = k3_chipinfo_variant_to_sr(partno_id, variant, soc_dev_attr); >> + if (partno_id == JTAG_ID_PARTNO_AM62PX) { >> + ret = regmap_read(regmap, CTRLMMR_WKUP_JTAGID_REG + >> + CTRLMMR_WKUP_GP_SW1_OFFSET, &gp_sw1_val); > > This is wrong, you cannot read from the register GP_SW1 (offset 544). In DT > the region is 4 bytes long (reg = <0x14 0x4>;). > > This only worked in your testing because the above ioremap_resource() > has to > map in page sized(4K) chunks and we didn't set max_register in our > regmap_config > so no bounds checking is done. If we fix either of the above then this read > will stop working. > > So yes you'll have to make DT changes and fight it out with Krzysztof. My > suggestion is to make a efuse region for the 3 GPSW registers and use a > phandle from this node to fetch the extra info you need to get revision. Sure I also believe that is the correct implementation and is actually the way I approached the issue in v1. But it seems like Krzysztof will not take that implementation [0] https://lore.kernel.org/linux-mmc/736f09e0-075a-48e0-9b32-6b8805a7ee2a@kernel.org/ so what to do then.... ~ Judith ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] mmc: sdhci_am654: Disable HS400 for AM62P SR1.0 and SR1.1 2025-08-07 22:51 [PATCH v2 0/2] Add support for AM62P SR1.2 Judith Mendez 2025-08-07 22:51 ` [PATCH v2 1/2] soc: ti: k3-socinfo: Add support for AM62P variants Judith Mendez @ 2025-08-07 22:51 ` Judith Mendez 2025-08-08 13:38 ` Judith Mendez 1 sibling, 1 reply; 6+ messages in thread From: Judith Mendez @ 2025-08-07 22:51 UTC (permalink / raw) To: Judith Mendez, Adrian Hunter, Ulf Hansson, Nishanth Menon, Santosh Shilimkar Cc: linux-mmc, linux-kernel, linux-arm-kernel, Andrew Davis This adds SDHCI_AM654_QUIRK_DISABLE_HS400 quirk which shall be used to disable HS400 support. AM62P SR1.0 and SR1.1 do not support HS400 due to errata i2458 [0] so disable HS400 for these SoC revisions. [0] https://www.ti.com/lit/er/sprz574a/sprz574a.pdf Signed-off-by: Judith Mendez <jm@ti.com> --- drivers/mmc/host/sdhci_am654.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index e4fc345be7e5..dc4975514847 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -156,6 +156,7 @@ struct sdhci_am654_data { #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) #define SDHCI_AM654_QUIRK_SUPPRESS_V1P8_ENA BIT(1) +#define SDHCI_AM654_QUIRK_DISABLE_HS400 BIT(2) }; struct window { @@ -765,6 +766,7 @@ static int sdhci_am654_init(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); + struct device *dev = mmc_dev(host->mmc); u32 ctl_cfg_2 = 0; u32 mask; u32 val; @@ -820,6 +822,12 @@ static int sdhci_am654_init(struct sdhci_host *host) if (ret) goto err_cleanup_host; + if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_DISABLE_HS400 && + host->mmc->caps2 & (MMC_CAP2_HS400 | MMC_CAP2_HS400_ES)) { + dev_err(dev, "Disable descoped HS400 mode for this silicon revision\n"); + host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); + } + ret = __sdhci_add_host(host); if (ret) goto err_cleanup_host; @@ -883,6 +891,12 @@ static int sdhci_am654_get_of_property(struct platform_device *pdev, return 0; } +static const struct soc_device_attribute sdhci_am654_descope_hs400[] = { + { .family = "AM62PX", .revision = "SR1.0" }, + { .family = "AM62PX", .revision = "SR1.1" }, + { /* sentinel */ } +}; + static const struct of_device_id sdhci_am654_of_match[] = { { .compatible = "ti,am654-sdhci-5.1", @@ -970,6 +984,10 @@ static int sdhci_am654_probe(struct platform_device *pdev) if (ret) return dev_err_probe(dev, ret, "parsing dt failed\n"); + soc = soc_device_match(sdhci_am654_descope_hs400); + if (soc) + sdhci_am654->quirks |= SDHCI_AM654_QUIRK_DISABLE_HS400; + host->mmc_host_ops.start_signal_voltage_switch = sdhci_am654_start_signal_voltage_switch; host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; -- 2.49.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/2] mmc: sdhci_am654: Disable HS400 for AM62P SR1.0 and SR1.1 2025-08-07 22:51 ` [PATCH v2 2/2] mmc: sdhci_am654: Disable HS400 for AM62P SR1.0 and SR1.1 Judith Mendez @ 2025-08-08 13:38 ` Judith Mendez 0 siblings, 0 replies; 6+ messages in thread From: Judith Mendez @ 2025-08-08 13:38 UTC (permalink / raw) To: Adrian Hunter, Ulf Hansson, Nishanth Menon, Santosh Shilimkar Cc: linux-mmc, linux-kernel, linux-arm-kernel, Andrew Davis Hi all, On 8/7/25 5:51 PM, Judith Mendez wrote: > This adds SDHCI_AM654_QUIRK_DISABLE_HS400 quirk which shall be used > to disable HS400 support. AM62P SR1.0 and SR1.1 do not support HS400 > due to errata i2458 [0] so disable HS400 for these SoC revisions. > > [0] https://www.ti.com/lit/er/sprz574a/sprz574a.pdf > Signed-off-by: Judith Mendez <jm@ti.com> > --- > drivers/mmc/host/sdhci_am654.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c > index e4fc345be7e5..dc4975514847 100644 > --- a/drivers/mmc/host/sdhci_am654.c > +++ b/drivers/mmc/host/sdhci_am654.c > @@ -156,6 +156,7 @@ struct sdhci_am654_data { > > #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) > #define SDHCI_AM654_QUIRK_SUPPRESS_V1P8_ENA BIT(1) > +#define SDHCI_AM654_QUIRK_DISABLE_HS400 BIT(2) > }; > > struct window { > @@ -765,6 +766,7 @@ static int sdhci_am654_init(struct sdhci_host *host) > { > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); > + struct device *dev = mmc_dev(host->mmc); > u32 ctl_cfg_2 = 0; > u32 mask; > u32 val; > @@ -820,6 +822,12 @@ static int sdhci_am654_init(struct sdhci_host *host) > if (ret) > goto err_cleanup_host; > > + if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_DISABLE_HS400 && > + host->mmc->caps2 & (MMC_CAP2_HS400 | MMC_CAP2_HS400_ES)) { > + dev_err(dev, "Disable descoped HS400 mode for this silicon revision\n"); Forgot to switch to dev_info, so will respin the series one more time. Sorry for the noise. ~ Judith ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-08-08 14:54 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-08-07 22:51 [PATCH v2 0/2] Add support for AM62P SR1.2 Judith Mendez 2025-08-07 22:51 ` [PATCH v2 1/2] soc: ti: k3-socinfo: Add support for AM62P variants Judith Mendez 2025-08-08 13:50 ` Andrew Davis 2025-08-08 14:51 ` Judith Mendez 2025-08-07 22:51 ` [PATCH v2 2/2] mmc: sdhci_am654: Disable HS400 for AM62P SR1.0 and SR1.1 Judith Mendez 2025-08-08 13:38 ` Judith Mendez
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