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[61.92.221.177]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-b422bb1133fsm23585496a12.56.2025.08.11.06.55.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 06:55:20 -0700 (PDT) From: Nick Chan Subject: [PATCH v8 00/21] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Date: Mon, 11 Aug 2025 21:54:32 +0800 Message-Id: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIABj2mWgC/3XPQWrDMBAF0KsErasijSRr3FXvEbqQR6NEEMfGb k1K8N0rB0psly7/wPv8uYuRh8yjeDvcxcBTHnN3LQFfDoLO4XpimWPJAhQ4BVrL0PcXltS3X9I FF0wMprZoRAH9wCnfHmXHj5LPefzshu9H96SX628NrGsmLZVMSD5BIO2teT+1IV9eqWvFUjPBm poNhULRN6bStQFG3FPzPzWFNuwThsgRddpTu6Z2Q+0yOFFQbJ22nvfUrSjghrpCa9ZgKQJytHt aPalVfkOrQgMjQQJw9Hewf1Kn1Yb65ddY7tRU5ECt6TzPP8dqajwGAgAA X-Change-ID: 20250211-apple-cpmu-5a5a3da39483 To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan , Krzysztof Kozlowski , Ivaylo Ivanov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4373; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=+LAKu174f1xhSbC2VdiHkWIZYXz3wYKQPJAQC4FzNig=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBomfZAzeYECu3q9NXPYbpcYcvwUCODSxZ5a4119 wtG+Jdk0MSJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaJn2QAAKCRABygi3psUI JIh2EACPm7iZczQOtNsl2grpezfen4As7n0d//LN0qy3Ld3fMEkyBoW9c5vVIsSm7X03a35pPtq 3a3dIbo5xCsN61OmqliYDNotIpnMXzslz+7jtgdfTdM/qygjXB0q/ZEUQpSUO/Eg/G1JeV5QsAI iBdrY0BaokZnPbg13soaR9dO9r8rWlEpHkzj4XOwiD3gvZ/sFjKSJGnMEsm0MQgxpFVc7cty2sz 9C2QXBvMXSUjFVzQCIPsrj50Y08lfpL72kadxbGolxpe2x4/zfTIGS7oJhz4smU54IMakcwznjl VebELeykl8bm4BDv/m/RPz9KgebuabPPi4/WyQGYkMfj2WTY8RObTmg9l8gbneuM2D132ZruiON QxNcXSlseDl5TBIWRcXkrw0DlHvxAsw+OTqIY/EOV0+ih81PSQHtVxx1IfgKPY7P/U/v0M1GioU FG6UxNVff6odUQu7OLONzY0Twmc7tCgOiwm2BQDHnDLmSgsxHeeVbPmLKrxmQ0mg6QAfNLT1Hcu TEPOsKAm8CR5EO6d6ERkN1hYsrWGOqOR3dPU4fINpCdEkBbt+CouNYtPkdZE5SSL5KKYezyDaOb XPUA3ZpMxMKYaAD7FZEHxwj3kOf39SJxxZ/KMsSRn+T1WkXqR4hZ65wmcz5W4894H9poMX4T6sV aiBYe2hh5qgTWXw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250811_065521_803882_D8FE5E6B X-CRM114-Status: GOOD ( 15.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series adds support for the CPU PMU in the older Apple A7-A11, T2 SoCs. These PMUs may have a different event layout, less counters, or deliver their interrupts via IRQ instead of a FIQ. Since some of those older SoCs support 32-bit EL0, counting for 32-bit EL0 also need to be enabled by the driver where applicable. Patch 1 adds the DT bindings. Patch 2-7 prepares the driver to allow adding support for those older SoCs. Patch 8-12 adds support for the older SoCs. Patch 13-21 are the DT changes. Signed-off-by: Nick Chan --- Changes in v8: - Rebased on top of v6.17-rc1 - Collect Ivaylo's Tested-by - Drop #define PMCR1_COUNT_A64_EL3_0_7 - Reword reason to not initialize PMUv3 remap in EL1 - Link to v7: https://lore.kernel.org/r/20250510-apple-cpmu-v7-0-bd505cb6c520@gmail.com Changes in v7: - Fix a W=1 compile warning in apple_pmu_get_event_idx() as appearently using GENMASK() in a function prototype causes a warning in GCC. - Link to v6: https://lore.kernel.org/r/20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com Changes in v6: - Rebased on top of v6.15-rc1 (Conflict with FEAT_PMUv3 support for KVM on Apple Hardware) - Add patch to skip initialization of PMUv3 remap in EL1 even though not strictly needed - Include DT patches - Link to v5: https://lore.kernel.org/r/20250228-apple-cpmu-v5-0-9e124cd28ed4@gmail.com Changes in v5: - Slightly change "drivers/perf: apple_m1: Add Apple A11 Support", to keep things in chronological order. - Link to v4: https://lore.kernel.org/r/20250214-apple-cpmu-v4-0-ffca0e45147e@gmail.com Changes in v4: - Support per-implementation event attr group - Fix Apple A7 event attr groups - Link to v3: https://lore.kernel.org/r/20250213-apple-cpmu-v3-0-be7f8aded81f@gmail.com Changes in v3: - Configure PMC8 and PMC9 for 32-bit EL0 - Remove redundant _common suffix from shared functions - Link to v2: https://lore.kernel.org/r/20250213-apple-cpmu-v2-0-87b361932e88@gmail.com Changes in v2: - Remove unused flags parameter from apple_pmu_init_common() - Link to v1: https://lore.kernel.org/r/20250212-apple-cpmu-v1-0-f8c7f2ac1743@gmail.com --- Nick Chan (21): dt-bindings: arm: pmu: Add Apple A7-A11 SoC CPU PMU compatibles drivers/perf: apple_m1: Only init PMUv3 remap when EL2 is available drivers/perf: apple_m1: Support per-implementation event tables drivers/perf: apple_m1: Support a per-implementation number of counters drivers/perf: apple_m1: Support configuring counters for 32-bit EL0 drivers/perf: apple_m1: Support per-implementation PMU startup drivers/perf: apple_m1: Support per-implementation event attr group drivers/perf: apple_m1: Add Apple A7 support drivers/perf: apple_m1: Add Apple A8/A8X support drivers/perf: apple_m1: Add A9/A9X support drivers/perf: apple_m1: Add Apple A10/A10X/T2 Support drivers/perf: apple_m1: Add Apple A11 Support arm64: dts: apple: s5l8960x: Add CPU PMU nodes arm64: dts: apple: t7000: Add CPU PMU nodes arm64: dts: apple: t7001: Add CPU PMU nodes arm64: dts: apple: s800-0-3: Add CPU PMU nodes arm64: dts: apple: s8001: Add CPU PMU nodes arm64: dts: apple: t8010: Add CPU PMU nodes arm64: dts: apple: t8011: Add CPU PMU nodes arm64: dts: apple: t8012: Add CPU PMU nodes arm64: dts: apple: t8015: Add CPU PMU nodes Documentation/devicetree/bindings/arm/pmu.yaml | 6 + arch/arm64/boot/dts/apple/s5l8960x.dtsi | 8 + arch/arm64/boot/dts/apple/s800-0-3.dtsi | 8 + arch/arm64/boot/dts/apple/s8001.dtsi | 8 + arch/arm64/boot/dts/apple/t7000.dtsi | 8 + arch/arm64/boot/dts/apple/t7001.dtsi | 9 + arch/arm64/boot/dts/apple/t8010.dtsi | 8 + arch/arm64/boot/dts/apple/t8011.dtsi | 9 + arch/arm64/boot/dts/apple/t8012.dtsi | 8 + arch/arm64/boot/dts/apple/t8015.dtsi | 24 + arch/arm64/include/asm/apple_m1_pmu.h | 2 + drivers/perf/apple_m1_cpu_pmu.c | 807 +++++++++++++++++++++++-- 12 files changed, 870 insertions(+), 35 deletions(-) --- base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585 change-id: 20250211-apple-cpmu-5a5a3da39483 Best regards, -- Nick Chan