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Mon, 11 Aug 2025 15:47:43 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, pankaj.dubey@samsung.com, Shradha Todi Subject: [PATCH v3 12/12] arm64: dts: fsd: Add PCIe support for Tesla FSD SoC Date: Mon, 11 Aug 2025 21:16:38 +0530 Message-ID: <20250811154638.95732-13-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250811154638.95732-1-shradha.t@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CMS-MailID: 20250811154746epcas5p261ba0c811f9dd8748f8f241b76be6525 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154746epcas5p261ba0c811f9dd8748f8f241b76be6525 References: <20250811154638.95732-1-shradha.t@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250811_220242_472484_DF616E7D X-CRM114-Status: GOOD ( 13.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the support for PCIe controller driver and phy driver for Tesla FSD. It includes support for both RC and EP. Signed-off-by: Pankaj Dubey Signed-off-by: Shradha Todi --- arch/arm64/boot/dts/tesla/fsd-evb.dts | 34 +++++ arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 65 +++++++++ arch/arm64/boot/dts/tesla/fsd.dtsi | 147 +++++++++++++++++++++ 3 files changed, 246 insertions(+) diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts index 9ff22e1c8723..1b63c5d72d19 100644 --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts @@ -130,3 +130,37 @@ &serial_0 { &ufs { status = "okay"; }; + +&pcierc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_clkreq>, <&pcie1_wake>, <&pcie1_preset>, + <&pcie0_slot1>; +}; + +&pcieep2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_clkreq>, <&pcie1_wake>, <&pcie1_preset>, + <&pcie0_slot1>; +}; + +&pcierc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq>, <&pcie0_wake0>, <&pcie0_preset0>, + <&pcie0_slot0>; +}; + +&pcieep0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq>, <&pcie0_wake0>, <&pcie0_preset0>, + <&pcie0_slot0>; +}; + +&pcierc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq>, <&pcie0_wake1>, <&pcie0_preset0>; +}; + +&pcieep1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq>, <&pcie0_wake1>, <&pcie0_preset0>; +}; diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi index 6f4658f57453..fa99aa4b9906 100644 --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi @@ -120,6 +120,27 @@ eth0_mdio: eth0-mdio-pins { samsung,pin-pud = ; samsung,pin-drv = ; }; + + pcie1_clkreq: pcie1-clkreq-pins { + samsung,pins = "gpf6-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcie1_wake: pcie1-wake-pins { + samsung,pins = "gpf6-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcie1_preset: pcie1-preset-pins { + samsung,pins = "gpf6-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; }; &pinctrl_peric { @@ -493,6 +514,50 @@ eth1_mdio: eth1-mdio-pins { samsung,pin-pud = ; samsung,pin-drv = ; }; + + pcie0_clkreq: pcie0-clkreq-pins { + samsung,pins = "gpc8-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcie0_wake0: pcie0-wake0-pins { + samsung,pins = "gpc8-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcie0_preset0: pcie0-preset0-pins { + samsung,pins = "gpc8-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcie0_wake1: pcie0-wake1-pins { + samsung,pins = "gpc8-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcie0_slot0: pcie0-gpio22-pins { + samsung,pins = "gpg2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <1>; + }; + + pcie0_slot1: pcie0-gpio23-pins { + samsung,pins = "gpg2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <1>; + }; }; &pinctrl_pmu { diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index a5ebb3f9b18f..8ed8d2131855 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -1009,6 +1009,16 @@ ethernet1: ethernet@14300000 { status = "disabled"; }; + pciephy0: pcie-phy@15080000 { + compatible = "tesla,fsd-pcie-phy0"; + reg = <0x0 0x15080000 0x0 0x2000>, + <0x0 0x150a0000 0x0 0x1000>; + #phy-cells = <0>; + samsung,pmu-syscon = <&pmu_system_controller>; + samsung,fsys-sysreg = <&sysreg_fsys0>; + status = "disabled"; + }; + ufs: ufs@15120000 { compatible = "tesla,fsd-ufs"; reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */ @@ -1057,6 +1067,143 @@ ethernet0: ethernet@15300000 { iommus = <&smmu_fsys0 0x0 0x1>; status = "disabled"; }; + + pcierc2: pcie@15400000 { + compatible = "tesla,fsd-pcie"; + reg = <0x0 0x15400000 0x0 0x2000>, + <0x0 0x15090000 0x0 0x1000>, + <0x0 0x15800000 0x0 0x1000>; + reg-names = "dbi", "elbi", "config"; + ranges = <0x82000000 0 0x15801000 0 0x15801000 0 0xffefff>; + clocks = <&clock_fsys0 PCIE_SUBCTRL_INST0_AUX_CLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_DBI_ACLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_SLV_ACLK_SOC>; + clock-names = "aux", "dbi", "mstr", "slv"; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + device_type = "pci"; + interrupts = ; + num-lanes = <4>; + phys = <&pciephy0>; + iommu-map = <0x0 &smmu_fsys0 0x4 0x10000>; + iommu-map-mask = <0x0>; + samsung,syscon-pcie = <&sysreg_fsys0 0x434>; + status = "disabled"; + }; + + pcieep2: pcie-ep@15400000 { + compatible = "tesla,fsd-pcie-ep"; + reg = <0x0 0x15090000 0x0 0x1000>, + <0x0 0x15400000 0x0 0x2000>, + <0x0 0x15402000 0x0 0x80>, + <0x0 0x15800000 0x0 0xff0000>; + reg-names = "elbi", "dbi", "dbi2", "addr_space"; + clocks = <&clock_fsys0 PCIE_SUBCTRL_INST0_AUX_CLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_DBI_ACLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_SLV_ACLK_SOC>; + clock-names = "aux", "dbi", "mstr", "slv"; + num-lanes = <4>; + phys = <&pciephy0>; + samsung,syscon-pcie = <&sysreg_fsys0 0x434>; + status = "disabled"; + }; + + pciephy1: pcie-phy@16880000 { + compatible = "tesla,fsd-pcie-phy1"; + reg = <0x0 0x16880000 0x0 0x2000>, + <0x0 0x16860000 0x0 0x1000>; + #phy-cells = <0>; + samsung,pmu-syscon = <&pmu_system_controller>; + samsung,fsys-sysreg = <&sysreg_fsys1>; + status = "disabled"; + }; + + pcierc0: pcie@16a00000 { + compatible = "tesla,fsd-pcie"; + reg = <0x0 0x16a00000 0x0 0x2000>, + <0x0 0x168b0000 0x0 0x1000>, + <0x0 0x17000000 0x0 0x1000>; + reg-names = "dbi", "elbi", "config"; + ranges = <0x82000000 0 0x17001000 0 0x17001000 0 0xffefff>; + clocks = <&clock_fsys1 PCIE_LINK0_IPCLKPORT_AUX_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_DBI_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_MSTR_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_SLV_ACLK>; + clock-names = "aux", "dbi", "mstr", "slv"; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + device_type = "pci"; + interrupts = ; + num-lanes = <4>; + phys = <&pciephy1>; + iommu-map = <0x0 &smmu_imem 0x0 0x10000>; + iommu-map-mask = <0x0>; + samsung,syscon-pcie = <&sysreg_fsys1 0x50c>; + status = "disabled"; + }; + + pcieep0: pcie-ep@16a00000 { + compatible = "tesla,fsd-pcie-ep"; + reg = <0x0 0x168b0000 0x0 0x1000>, + <0x0 0x16a00000 0x0 0x2000>, + <0x0 0x16a02000 0x0 0x80>, + <0x0 0x17000000 0x0 0xff0000>; + reg-names = "elbi", "dbi", "dbi2", "addr_space"; + clocks = <&clock_fsys1 PCIE_LINK0_IPCLKPORT_AUX_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_DBI_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_MSTR_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_SLV_ACLK>; + clock-names = "aux", "dbi", "mstr", "slv"; + num-lanes = <4>; + phys = <&pciephy1>; + samsung,syscon-pcie = <&sysreg_fsys1 0x50c>; + status = "disabled"; + }; + + pcierc1: pcie@16b00000 { + compatible = "tesla,fsd-pcie"; + reg = <0x0 0x16b00000 0x0 0x2000>, + <0x0 0x168c0000 0x0 0x1000>, + <0x0 0x18000000 0x0 0x1000>; + reg-names = "dbi", "elbi", "config"; + ranges = <0x82000000 0 0x18001000 0 0x18001000 0 0xffefff>; + clocks = <&clock_fsys1 PCIE_LINK1_IPCLKPORT_AUX_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_DBI_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_MSTR_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_SLV_ACLK>; + clock-names = "aux", "dbi", "mstr", "slv"; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + device_type = "pci"; + interrupts = ; + num-lanes = <4>; + phys = <&pciephy1>; + samsung,syscon-pcie = <&sysreg_fsys1 0x510>; + status = "disabled"; + }; + + pcieep1: pcie-ep@16b00000 { + compatible = "tesla,fsd-pcie-ep"; + reg = <0x0 0x168c0000 0x0 0x1000>, + <0x0 0x16b00000 0x0 0x2000>, + <0x0 0x16b02000 0x0 0x80>, + <0x0 0x18000000 0x0 0xff0000>; + reg-names = "elbi", "dbi", "dbi2", "addr_space"; + clocks = <&clock_fsys1 PCIE_LINK1_IPCLKPORT_AUX_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_DBI_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_MSTR_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_SLV_ACLK>; + clock-names = "aux", "dbi", "mstr", "slv"; + num-lanes = <4>; + phys = <&pciephy1>; + samsung,syscon-pcie = <&sysreg_fsys1 0x510>; + status = "disabled"; + }; }; }; -- 2.49.0