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Mon, 11 Aug 2025 15:47:18 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, pankaj.dubey@samsung.com, Shradha Todi Subject: [PATCH v3 06/12] dt-bindings: PCI: Split exynos host into two files Date: Mon, 11 Aug 2025 21:16:32 +0530 Message-ID: <20250811154638.95732-7-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250811154638.95732-1-shradha.t@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CMS-MailID: 20250811154721epcas5p26c9e2880ca55a470f595d914b4030745 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154721epcas5p26c9e2880ca55a470f595d914b4030745 References: <20250811154638.95732-1-shradha.t@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250811_220224_329652_3B903554 X-CRM114-Status: GOOD ( 20.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The current Exynos PCIe yaml binding file is hard to reuse by other Samsung SoCs. Refactoring it by: - Moving common Samsung PCIe properties into samsung,exynos-pcie.yaml - Creating a dedicated samsung,exynos5433-pcie.yaml file for properties and constraints specific to the Exynos5433 SoC Signed-off-by: Shradha Todi --- .../bindings/pci/samsung,exynos-pcie.yaml | 70 +-------------- .../bindings/pci/samsung,exynos5433-pcie.yaml | 89 +++++++++++++++++++ 2 files changed, 91 insertions(+), 68 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos5433-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml index f20ed7e709f7..fd0b97b30821 100644 --- a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml @@ -11,7 +11,7 @@ maintainers: - Jaehoon Chung description: |+ - Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare + Samsung SoCs PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. @@ -19,9 +19,6 @@ allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# properties: - compatible: - const: samsung,exynos5433-pcie - reg: items: - description: Data Bus Interface (DBI) registers. @@ -37,83 +34,20 @@ properties: interrupts: maxItems: 1 - clocks: - items: - - description: PCIe bridge clock - - description: PCIe bus clock - - clock-names: - items: - - const: pcie - - const: pcie_bus - phys: maxItems: 1 - vdd10-supply: - description: - Phandle to a regulator that provides 1.0V power to the PCIe block. - - vdd18-supply: - description: - Phandle to a regulator that provides 1.8V power to the PCIe block. - - num-lanes: - const: 1 - - num-viewport: - const: 3 - required: - reg - reg-names - interrupts - "#address-cells" - "#size-cells" - - "#interrupt-cells" - - interrupt-map - - interrupt-map-mask - ranges - - bus-range - device_type - num-lanes - - num-viewport - clocks - clock-names - phys - - vdd10-supply - - vdd18-supply - -unevaluatedProperties: false - -examples: - - | - #include - #include - #include - pcie: pcie@15700000 { - compatible = "samsung,exynos5433-pcie"; - reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>; - reg-names = "dbi", "elbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - device_type = "pci"; - interrupts = ; - clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>; - clock-names = "pcie", "pcie_bus"; - phys = <&pcie_phy>; - pinctrl-0 = <&pcie_bus &pcie_wlanen>; - pinctrl-names = "default"; - num-lanes = <1>; - num-viewport = <3>; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, - <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; - vdd10-supply = <&ldo6_reg>; - vdd18-supply = <&ldo7_reg>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; - }; -... +additionalProperties: true diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5433-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos5433-pcie.yaml new file mode 100644 index 000000000000..1fb2c32899c4 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/samsung,exynos5433-pcie.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/samsung,exynos5433-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos5433 SoC PCIe Host Controller + +maintainers: + - Marek Szyprowski + - Jaehoon Chung + +description: + Exynos5433 SoCs PCIe host controller inherits all the + common properties defined in samsung,exynos-pcie.yaml + +allOf: + - $ref: /schemas/pci/samsung,exynos-pcie.yaml# + +properties: + compatible: + const: samsung,exynos5433-pcie + + clocks: + items: + - description: PCIe bridge clock + - description: PCIe bus clock + + clock-names: + items: + - const: pcie + - const: pcie_bus + + num-lanes: + const: 1 + + num-viewport: + const: 3 + + vdd10-supply: + description: + phandle to a regulator that provides 1.0v power to the pcie block + + vdd18-supply: + description: + phandle to a regulator that provides 1.8v power to the pcie block + +required: + - "#interrupt-cells" + - interrupt-map + - interrupt-map-mask + - bus-range + - num-viewport + - vdd10-supply + - vdd18-supply + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + pcie: pcie@15700000 { + compatible = "samsung,exynos5433-pcie"; + reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>; + reg-names = "dbi", "elbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupts = ; + clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>; + clock-names = "pcie", "pcie_bus"; + phys = <&pcie_phy>; + pinctrl-0 = <&pcie_bus &pcie_wlanen>; + pinctrl-names = "default"; + num-lanes = <1>; + num-viewport = <3>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, + <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; + vdd10-supply = <&ldo6_reg>; + vdd18-supply = <&ldo7_reg>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; + }; +... -- 2.49.0