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Mon, 11 Aug 2025 15:47:27 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, pankaj.dubey@samsung.com, Shradha Todi Subject: [PATCH v3 08/12] dt-bindings: phy: Add PCIe PHY support for FSD SoC Date: Mon, 11 Aug 2025 21:16:34 +0530 Message-ID: <20250811154638.95732-9-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250811154638.95732-1-shradha.t@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CMS-MailID: 20250811154729epcas5p456ddb0d1ba34b992204f54724b57a401 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154729epcas5p456ddb0d1ba34b992204f54724b57a401 References: <20250811154638.95732-1-shradha.t@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250811_220230_031837_DB58C6ED X-CRM114-Status: GOOD ( 14.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Since Tesla FSD SoC uses Samsung PCIe PHY, add support in exynos PCIe PHY bindings. In Tesla FSD SoC, the two PHY instances, although having identical hardware design and register maps, are placed in different locations (Placement and routing) inside the SoC and have distinct PHY-to-Controller topologies. (One instance is connected to two PCIe controllers, while the other is connected to only one). As a result, they experience different analog environments, including varying channel losses and noise profiles. Since these PHYs lack internal adaptation mechanisms and f/w based tuning, manual register programming is required for analog tuning. To ensure optimal signal integrity, it is essential to use different register values for each PHY instance, despite their identical hardware design. This is because the same register values may not be suitable for both instances due to their differing environments and topologies. Due to this, we are using two PHY compatibles for different PHY instances. Signed-off-by: Shradha Todi --- .../bindings/phy/samsung,exynos-pcie-phy.yaml | 27 +++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml index 41df8bb08ff7..6295472696db 100644 --- a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml @@ -15,10 +15,14 @@ properties: const: 0 compatible: - const: samsung,exynos5433-pcie-phy + enum: + - samsung,exynos5433-pcie-phy + - tesla,fsd-pcie-phy0 + - tesla,fsd-pcie-phy1 reg: - maxItems: 1 + minItems: 1 + maxItems: 2 samsung,pmu-syscon: $ref: /schemas/types.yaml#/definitions/phandle @@ -30,6 +34,25 @@ properties: description: phandle for FSYS sysreg interface, used to control sysreg registers bits for PCIe PHY +allOf: + - if: + properties: + compatible: + contains: + enum: + - tesla,fsd-pcie-phy0 + - tesla,fsd-pcie-phy1 + then: + properties: + reg: + items: + - description: PHY + - description: PCS + else: + properties: + reg: + maxItems: 1 + required: - "#phy-cells" - compatible -- 2.49.0