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Tue, 12 Aug 2025 15:50:55 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 6C6BD40048; Tue, 12 Aug 2025 15:49:24 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C98E37835C8; Tue, 12 Aug 2025 15:48:59 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 15:48:59 +0200 From: Raphael Gallais-Pou Subject: [PATCH v2 00/13] Enable display support for STM32MP25 Date: Tue, 12 Aug 2025 15:48:57 +0200 Message-ID: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAElGm2gC/13MywqDMBCF4VeRWXckCYmXrnyP4kLipM5CUzIiF vHdm9pdl/+B8x0glJgE7sUBiTYWjksOcyvAT8PyJOQxNxhlnKp0jWOacWbxuNC+oh2CVZXX3ro A+fNKFHi/vEefe2JZY3pf/Ka/60+qjfuTNo0KB9c2tqHK+NB2IYqUspY+ztCf5/kBvG0dVKwAA AA= X-Change-ID: 20250617-drm-misc-next-4af406c1c45f To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-Originating-IP: [10.130.74.180] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_07,2025-08-11_01,2025-03-28_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250812_145119_209350_4CE0C1EE X-CRM114-Status: GOOD ( 16.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series aims to add and enable sufficient LVDS display support for STM32MP257F-EV1 board. LVDS is the default use case to drive a display panel on STM32MP257F-EV, even though DSI panels will be supported in the near future. The LTDC needs a pixel rate in sync with the bridge currently in use. For that both DSI and LVDS bridges need to declare an internal clock and become clock provider to the mux. The mux then selects the reference clock for the LTDC pixel rate generation. For now this mux is handled internally in the LTDC, while waiting for the STM32 clock framework to merge a 'clk-mux' based on the SYSCFG. This explains the link done in the patch [7/8] between the LVDS, providing the reference clock for the LTDC internals. +----------+ |\ | DSI PHY |------------->| \ +------------+ | |ck_dsi_phy | | | | +----------+ | |--------->| LTDC | +----------+ | |pixel_clk | | | LVDS PHY |------------->| | +------------+ | |clk_pix_lvds | | +----------+ | | | | ck_ker_ltdc ------------>| / |/| └- SYSCFG Clock selection applies as follow: - 0b00: Selects ck_dsi_phy - 0b01: Selects clk_pix_lvds - 0b10: Selects ck_ker_ltdc (for parallel or DSI display). - 0b11: Reserved The reset value of the register controlling the mux is 0b01, meaning that the default clock assigned is the clk_pix_lvds. This causes two things: - In order to get basic display on the LVDS encoder, like intended, nothing has to be done on this mux within the LTDC driver (which for now explains the unused syscfg phandle on the LTDC node in the device-tree). - 'pixel_clk' is dependent from 'clk_pix_lvds' because of the LTDC clock domains. They also need to be sync to get a coherent pixel rate though the display clock tree (which explains the LVDS phandle on the LTDC node in the device-tree). Signed-off-by: Raphael Gallais-Pou --- Changes in v2: - Documentation: - Add support for new compatible "st,stm32mp255-lvds" - Change LTDC compatible for SoC compliant one - Make clearer LTDC clock-names property - Devicetree: - Change compatible according to the documentation - Change clock and clock-names order to match documentation (and avoid warnings) - Drivers: - Change LTDC compatible - Add Rob's trailer where relevant - Link to v1: https://lore.kernel.org/r/20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com --- Raphael Gallais-Pou (11): dt-bindings: display: st: add new compatible to LTDC device dt-bindings: display: st,stm32-ltdc: add access-controllers property dt-bindings: display: st: add new compatible to LVDS device dt-bindings: display: st,stm32mp25-lvds: add access-controllers property dt-bindings: display: st,stm32mp25-lvds: add power-domains property dt-bindings: arm: stm32: add required #clock-cells property arm64: dts: st: add ltdc support on stm32mp251 arm64: dts: st: add lvds support on stm32mp255 arm64: dts: st: add clock-cells to syscfg node on stm32mp251 arm64: dts: st: enable display support on stm32mp257f-ev1 board arm64: dts: st: add loopback clocks on LTDC node Yannick Fertre (2): drm/stm: ltdc: support new hardware version for STM32MP25 SoC drm/stm: ltdc: handle lvds pixel clock .../bindings/arm/stm32/st,stm32-syscon.yaml | 31 ++++++--- .../devicetree/bindings/display/st,stm32-ltdc.yaml | 33 ++++++++- .../bindings/display/st,stm32mp25-lvds.yaml | 14 +++- arch/arm64/boot/dts/st/stm32mp251.dtsi | 19 ++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 19 +++++- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 79 ++++++++++++++++++++++ drivers/gpu/drm/stm/drv.c | 11 ++- drivers/gpu/drm/stm/ltdc.c | 57 +++++++++++++++- drivers/gpu/drm/stm/ltdc.h | 6 ++ 9 files changed, 251 insertions(+), 18 deletions(-) --- base-commit: e48123c607a0db8b9ad02f83c8c3d39918dbda06 change-id: 20250617-drm-misc-next-4af406c1c45f Best regards, -- Raphael Gallais-Pou