Re: FYI: i.MX8MP ISP (RKISP1) MI registers corruption: resolved

[Laurent Pinchart <laurent.pinchart@ideasonboard.com>]

Hi Krzysztof,

On Tue, Aug 12, 2025 at 07:54:46AM +0200, Krzysztof Hałasa wrote:
> Hi Stefan et al,
> 
> BTW I've added Lucas Stach and Shawn Guo to "Cc" list.
> 
> The problem is the CPU core power supply voltage :-)

Ah, the dreadful overdrive mode.

> - while the reference manual specifies the max ISP and MEDIA clocks at
>   500 MHz, the datasheets show this requires the "overdrive" mode =
>   increased CPU power supply voltage. In "normal" mode the ISPs are
>   limited to 400 MHz (there are other limits, too).
> 
> - I've tried lowering the clock rate after booting the systems (with
>   a CCM register write), but it didn't fix the problem. I guess some
>   reset logic is affected here, and the (lower) clock rate must be set
>   right from the start, in the DT.

That's interesting. I wouldn't have expected that.

> - anyway, lowering the frequencies of ISP and MEDIA root clocks fixes
>   the ISP2 MI corruption. I'm currently investigating PMIC settings
>   (both my Compulab and SolidRun modules use PCA9450C PMICs), so perhaps
>   I'll be able to use the higher 500 MHz clocks. It doesn't matter much,
>   though.
> 
> - the question is if we should lower the clocks in the main imx8mp.dtsi
>   DT file, or the overdrive mode should stay there, and the changes
>   should be made to the individual board files, or maybe the U-Boot
>   configs (PMIC output voltages) should be changed etc.

I think it would make sense to lower the default clock frequencies, and
provide an overlay to enable overdrive mode.

It's also interesting that the issue only affected the second ISP, as
the first one should also be limited to 400 MHz in normal mode.

-- 
Regards,

Laurent Pinchart