From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8FAA0CA0EE0 for ; Wed, 13 Aug 2025 15:07:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=/xup+Q4w/5VrYct9OQiMGtseZ+FfWwPJHt1ncLSJ/hM=; b=4ckcafEI4NSMqsARfVY3JGIybu jkp3j6yvFyzRyFuigwHnhzE5RXYH33kFbPvcAtgB/LHR2a00SfRp6koyrL+hzi7X3fpHi8Lf6DTB7 UHhIXAJ3AWehXs2rYlWYXpY1CZ8/aCBa6XWcf1oQ2zNvum3n9HRc4d+XXQEWh4g++Al5+8HTI3/1x KOX1PCAmYKhUA7KIaWANTZ7NmbTexE974Q3nyphMDo3HQ2lElpdAvcsyB12i1n/Mobz5vaKwk532h njMAM+PK7VyGq8srpPhAAKJTUnmFQENK0wULRQmBsAoB0ij/N6slnqmjEoiwMxRcZZt33TVce91W7 tdw8dZ8g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1umD4A-0000000E89L-1ZqD; Wed, 13 Aug 2025 15:07:02 +0000 Received: from tor.source.kernel.org ([172.105.4.254]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1umCtJ-0000000E4jO-2JLR for linux-arm-kernel@lists.infradead.org; Wed, 13 Aug 2025 14:55:49 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 86560601FB; Wed, 13 Aug 2025 14:55:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A4AEAC4AF0B; Wed, 13 Aug 2025 14:55:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755096947; bh=VH0N7W47+kOQX4MCst8bkGtFUp56xeT53SSsWcTl1lA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j54Zd/IRCdHbdteiJ/3WB5SmJxLTENox/6+0h8gnY3oDL7I+CnDTpEYMQO9ntpzLD Uw0ZjCwC78QtmvVGClqZA+XJ4q4aKlHQa7njPt7OQq6ZTPuqTB6hGRaj+my1wbwra1 WQ94vtqT4OBZX8Vx0/L6oxUfFswvc1Gho/kuS33P+qmC2I/vH8copLv5r9Ru9zgE1A cld74mX1dawuaMGvM7zIwzMhy1ubTBoWmJ2IJA1w75nVBoVL1s2en+JWfueSo8n5UW F6P+LHb4OJd1FUlPPln05QtnYCH1gpobIIloWGMeIq39Q6ah1dPqW1F9t7h+1aq0FW S6g4oj44JN5hg== Received: by wens.tw (Postfix, from userid 1000) id 1658D5FE8C; Wed, 13 Aug 2025 22:55:44 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v2 01/10] dt-bindings: net: sun8i-emac: Add A523 GMAC200 compatible Date: Wed, 13 Aug 2025 22:55:31 +0800 Message-Id: <20250813145540.2577789-2-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250813145540.2577789-1-wens@kernel.org> References: <20250813145540.2577789-1-wens@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Chen-Yu Tsai The Allwinner A523 SoC family has a second Ethernet controller, called the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for numbering. This controller, according to BSP sources, is fully compatible with a slightly newer version of the Synopsys DWMAC core. The glue layer around the controller is the same as found around older DWMAC cores on Allwinner SoCs. The only slight difference is that since this is the second controller on the SoC, the register for the clock delay controls is at a different offset. Last, the integration includes a dedicated clock gate for the memory bus and the whole thing is put in a separately controllable power domain. Add a compatible string entry for it, and work in the requirements for a second clock and a power domain. Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../net/allwinner,sun8i-a83t-emac.yaml | 81 ++++++++++++++++++- 1 file changed, 79 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml index 2ac709a4c472..b4358e6456fa 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -26,6 +26,9 @@ properties: - allwinner,sun50i-h616-emac0 - allwinner,sun55i-a523-gmac0 - const: allwinner,sun50i-a64-emac + - items: + - const: allwinner,sun55i-a523-gmac200 + - const: snps,dwmac-4.20a reg: maxItems: 1 @@ -37,14 +40,19 @@ properties: const: macirq clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 clock-names: - const: stmmaceth + minItems: 1 + maxItems: 2 phy-supply: description: PHY regulator + power-domains: + maxItems: 1 + syscon: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -191,6 +199,45 @@ allOf: - mdio-parent-bus - mdio@1 + - if: + properties: + compatible: + contains: + const: allwinner,sun55i-a523-gmac200 + then: + properties: + clocks: + minItems: 2 + clock-names: + items: + - const: stmmaceth + - const: mbus + tx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 700 + multipleOf: 100 + description: + External RGMII PHY TX clock delay chain value in ps. + rx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 3100 + multipleOf: 100 + description: + External RGMII PHY TX clock delay chain value in ps. + required: + - power-domains + else: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: stmmaceth + power-domains: false + + unevaluatedProperties: false examples: @@ -323,4 +370,34 @@ examples: }; }; + - | + ethernet@4510000 { + compatible = "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg = <0x04510000 0x10000>; + clocks = <&ccu 117>, <&ccu 79>; + clock-names = "stmmaceth", "mbus"; + resets = <&ccu 43>; + reset-names = "stmmaceth"; + interrupts = <0 47 4>; + interrupt-names = "macirq"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins>; + power-domains = <&pck600 4>; + syscon = <&syscon>; + phy-handle = <&ext_rgmii_phy_1>; + phy-mode = "rgmii-id"; + snps,fixed-burst; + snps,axi-config = <&gmac1_stmmac_axi_setup>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ext_rgmii_phy_1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; ... -- 2.39.5