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Thu, 14 Aug 2025 20:16:22 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 14 Aug 2025 20:16:21 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 14 Aug 2025 20:16:21 -0500 Received: from localhost (uda0133052.dhcp.ti.com [128.247.81.232]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57F1GLQh572247; Thu, 14 Aug 2025 20:16:21 -0500 Date: Thu, 14 Aug 2025 20:16:21 -0500 From: Nishanth Menon To: Randolph Sapp CC: , , , , , , , , , , , , , Michael Walle Subject: Re: [PATCH 2/3] arm64: dts: ti: k3-am62p-j722s: enable the bxs-4-64 Message-ID: <20250815011621.rrdurnk6ueexwldw@hertz> References: <20250808232522.1296240-1-rs@ti.com> <20250808232522.1296240-2-rs@ti.com> <20250813151721.nc5fr3qmro5grlda@steam> <20250813184229.dhgpqvi3b6aat46g@managing> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250814_181629_797424_F4DAC1DF X-CRM114-Status: GOOD ( 15.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 15:40-20250814, Randolph Sapp wrote: > On Wed Aug 13, 2025 at 1:42 PM CDT, Nishanth Menon wrote: > > On 12:56-20250813, Randolph Sapp wrote: > > [...] > > > >> >> + reg = <0x00 0x0fd80000 0x00 0x80000>; > >> >> + clocks = <&k3_clks 237 1>; > >> >> + clock-names = "core"; > >> >> + assigned-clocks = <&k3_clks 237 1>; > >> >> + assigned-clock-rates = <800000000>; > > > > btw, as per https://www.ti.com/lit/ds/symlink/tda4aen-q1.pdf (page 86) > > 720MHz when vdd_core is 0.75v (default) > > and 800MHz when vdd_core is 0.85v > > > > 0.85v is set in the board dts and higher OPPs are enabled depending on > > board capability. > > > > You might want to check the assigned-clock-rates based on data sheet, > > default should'nt need a assigned-clock-rate. > > Are you suggesting that we set assigned-clock-rates in the board dts instead, or > do you just want to do away with assigned-clock-rates in general and eat the > perf difference? The higher frequency is possible unless you know that the board is setup for the higher voltage. So, set it board device tree file. Look at what we did with OPP-High support on AM625 for example. That frequency can only be reliably achieved if vdd_core is 0.85v. And base SoC dtsi must assume safe default (min voltage of 0.75v) as the node is enabled by default. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D https://ti.com/opensource