[PATCH v7 0/6] thermal: renesas: Add support for RZ/G3E

[PATCH v7 0/6] thermal: renesas: Add support for RZ/G3E

[John Madieu]

This series adds support for the temperature sensor unit (TSU) found on the
Renesas RZ/G3E SoC.

The series consists of 5 patches (one of which is not related to the thermal
framework) that progressively add TSU support as follows:
- patch 1/6:    adds syscon/regmap support for accessing system controller
                registers, enabling access to TSU calibration values

- patch 2-6/6:  adds dt-bindings, actual driver, DT node, and config symbol.

Patch 1/6 has been duplicated at [1] in USB series. This series addresses comments
got from there.

Changes:

v1 -> v2
 * Fix yaml warnings from dt-binding
 * Update IRQ names to reflect TSU expectations

v2 -> v3
 * Remove useless 'renesas,tsu-operating-mode' property

v3 -> v4
 * Improve commit messages

v4 -> v5
 * Remove useless curly braces on single line-protected scoped guards

v5 -> v6
 * Minor typo fix
 * Constify regmap config in patch 1/5

v6 -> v7
 * Update DTS trim priperty name and specifier, updading the documentation
 accordingly
 * Refactor main driver: remove spinlock usage, using polling timeout as computed
 from datasheet. Also use polling for get_temp() while using IRQ for trip-point
 cross detection, and finally add both runtime and sleep PM support.
 * Add new patch to update sys #address-cells as trim specifier now requires an
 offet from sys base

Regards,

[1] https://lore.kernel.org/all/20250808061806.2729274-2-claudiu.beznea.uj@bp.renesas.com/


John Madieu (6):
  soc: renesas: rz-sysc: Add syscon/regmap support
  dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit
  thermal: renesas: rzg3e: Add thermal driver for the Renesas RZ/G3E SoC
  arm64: dts: renesas: r9a09g047: Add #address-cells property in sys
    node
  arm64: dts: renesas: r9a09g047: Add TSU node
  arm64: defconfig: Enable the Renesas RZ/G3E thermal driver

 .../thermal/renesas,r9a09g047-tsu.yaml        |  87 +++
 MAINTAINERS                                   |   7 +
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |  49 ++
 arch/arm64/configs/defconfig                  |   1 +
 drivers/soc/renesas/Kconfig                   |   1 +
 drivers/soc/renesas/r9a08g045-sysc.c          |   1 +
 drivers/soc/renesas/r9a09g047-sys.c           |   1 +
 drivers/soc/renesas/r9a09g057-sys.c           |   1 +
 drivers/soc/renesas/rz-sysc.c                 |  28 +-
 drivers/soc/renesas/rz-sysc.h                 |   2 +
 drivers/thermal/renesas/Kconfig               |   7 +
 drivers/thermal/renesas/Makefile              |   1 +
 drivers/thermal/renesas/rzg3e_thermal.c       | 575 ++++++++++++++++++
 13 files changed, 760 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
 create mode 100644 drivers/thermal/renesas/rzg3e_thermal.c

-- 
2.25.1

[PATCH v7 1/6] soc: renesas: rz-sysc: Add syscon/regmap support

[John Madieu]

The RZ/G3E system controller has various registers that control or report
some properties specific to individual IPs. The regmap is registered as a
syscon device to allow these IP drivers to access the registers through the
regmap API.

As other RZ SoCs might have custom read/write callbacks or max-offsets,
register a custom regmap configuration.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
[claudiu.beznea:
 - do not check the match->data validity in rz_sysc_probe() as it is
   always valid
 - dinamically allocate regmap_cfg]
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---

Changes:

v1 -> v2: no changes
v2 -> v3: no changes
v3 -> v4: no changes
v4 -> v5: no changes
v6: Addressed the review comments received at [1]
v7: As this is a duplicate of [2], address comment received there, that is,
    use kzalloc() + kfree() for regmap_cfg.

[1] https://lore.kernel.org/all/20250330214945.185725-2-john.madieu.xa@bp.renesas.com/
[2] https://lore.kernel.org/all/20250808061806.2729274-1-claudiu.beznea.uj@bp.renesas.com/

 drivers/soc/renesas/Kconfig          |  1 +
 drivers/soc/renesas/r9a08g045-sysc.c |  1 +
 drivers/soc/renesas/r9a09g047-sys.c  |  1 +
 drivers/soc/renesas/r9a09g057-sys.c  |  1 +
 drivers/soc/renesas/rz-sysc.c        | 28 +++++++++++++++++++++++++++-
 drivers/soc/renesas/rz-sysc.h        |  2 ++
 6 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 719b7f4f376f..c97e2a183388 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -449,6 +449,7 @@ config RST_RCAR
 
 config SYSC_RZ
 	bool "System controller for RZ SoCs" if COMPILE_TEST
+	select MFD_SYSCON
 
 config SYSC_R9A08G045
 	bool "Renesas System controller support for R9A08G045 (RZ/G3S)" if COMPILE_TEST
diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a08g045-sysc.c
index f4db1431e036..0504d4e68761 100644
--- a/drivers/soc/renesas/r9a08g045-sysc.c
+++ b/drivers/soc/renesas/r9a08g045-sysc.c
@@ -20,4 +20,5 @@ static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initc
 
 const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst = {
 	.soc_id_init_data = &rzg3s_sysc_soc_id_init_data,
+	.max_register = 0xe20,
 };
diff --git a/drivers/soc/renesas/r9a09g047-sys.c b/drivers/soc/renesas/r9a09g047-sys.c
index cd2eb7782cfe..2e8426c03050 100644
--- a/drivers/soc/renesas/r9a09g047-sys.c
+++ b/drivers/soc/renesas/r9a09g047-sys.c
@@ -64,4 +64,5 @@ static const struct rz_sysc_soc_id_init_data rzg3e_sys_soc_id_init_data __initco
 
 const struct rz_sysc_init_data rzg3e_sys_init_data = {
 	.soc_id_init_data = &rzg3e_sys_soc_id_init_data,
+	.max_register = 0x170c,
 };
diff --git a/drivers/soc/renesas/r9a09g057-sys.c b/drivers/soc/renesas/r9a09g057-sys.c
index 4c21cc29edbc..e3390e7c7fe5 100644
--- a/drivers/soc/renesas/r9a09g057-sys.c
+++ b/drivers/soc/renesas/r9a09g057-sys.c
@@ -64,4 +64,5 @@ static const struct rz_sysc_soc_id_init_data rzv2h_sys_soc_id_init_data __initco
 
 const struct rz_sysc_init_data rzv2h_sys_init_data = {
 	.soc_id_init_data = &rzv2h_sys_soc_id_init_data,
+	.max_register = 0x170c,
 };
diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c
index ffa65fb4dade..c06758faf19f 100644
--- a/drivers/soc/renesas/rz-sysc.c
+++ b/drivers/soc/renesas/rz-sysc.c
@@ -6,8 +6,10 @@
  */
 
 #include <linux/io.h>
+#include <linux/mfd/syscon.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
+#include <linux/regmap.h>
 #include <linux/sys_soc.h>
 
 #include "rz-sysc.h"
@@ -100,14 +102,23 @@ MODULE_DEVICE_TABLE(of, rz_sysc_match);
 
 static int rz_sysc_probe(struct platform_device *pdev)
 {
+	const struct rz_sysc_init_data *data;
 	const struct of_device_id *match;
 	struct device *dev = &pdev->dev;
+	struct regmap *regmap;
 	struct rz_sysc *sysc;
+	int ret;
+
+	struct regmap_config *regmap_cfg __free(kfree) = kzalloc(sizeof(*regmap_cfg), GFP_KERNEL);
+	if (!regmap_cfg)
+		return -ENOMEM;
 
 	match = of_match_node(rz_sysc_match, dev->of_node);
 	if (!match)
 		return -ENODEV;
 
+	data = match->data;
+
 	sysc = devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL);
 	if (!sysc)
 		return -ENOMEM;
@@ -117,7 +128,22 @@ static int rz_sysc_probe(struct platform_device *pdev)
 		return PTR_ERR(sysc->base);
 
 	sysc->dev = dev;
-	return rz_sysc_soc_init(sysc, match);
+	ret = rz_sysc_soc_init(sysc, match);
+	if (ret)
+		return ret;
+
+	regmap_cfg->name = "rz_sysc_regs";
+	regmap_cfg->reg_bits = 32;
+	regmap_cfg->reg_stride = 4;
+	regmap_cfg->val_bits = 32;
+	regmap_cfg->fast_io = true;
+	regmap_cfg->max_register = data->max_register;
+
+	regmap = devm_regmap_init_mmio(dev, sysc->base, regmap_cfg);
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	return of_syscon_register_regmap(dev->of_node, regmap);
 }
 
 static struct platform_driver rz_sysc_driver = {
diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h
index 56bc047a1bff..8eec355d5d56 100644
--- a/drivers/soc/renesas/rz-sysc.h
+++ b/drivers/soc/renesas/rz-sysc.h
@@ -34,9 +34,11 @@ struct rz_sysc_soc_id_init_data {
 /**
  * struct rz_sysc_init_data - RZ SYSC initialization data
  * @soc_id_init_data: RZ SYSC SoC ID initialization data
+ * @max_register: Maximum SYSC register offset to be used by the regmap config
  */
 struct rz_sysc_init_data {
 	const struct rz_sysc_soc_id_init_data *soc_id_init_data;
+	u32 max_register;
 };
 
 extern const struct rz_sysc_init_data rzg3e_sys_init_data;
-- 
2.25.1

Re: [PATCH v7 1/6] soc: renesas: rz-sysc: Add syscon/regmap support

[claudiu beznea]

On 8/18/25 19:28, John Madieu wrote:
> The RZ/G3E system controller has various registers that control or report
> some properties specific to individual IPs. The regmap is registered as a
> syscon device to allow these IP drivers to access the registers through the
> regmap API.
> 
> As other RZ SoCs might have custom read/write callbacks or max-offsets,
> register a custom regmap configuration.
> 
> Signed-off-by: John Madieu<john.madieu.xa@bp.renesas.com>
> [claudiu.beznea:
>   - do not check the match->data validity in rz_sysc_probe() as it is
>     always valid
>   - dinamically allocate regmap_cfg]
> Signed-off-by: Claudiu Beznea<claudiu.beznea.uj@bp.renesas.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S

Re: [PATCH v7 1/6] soc: renesas: rz-sysc: Add syscon/regmap support

[Geert Uytterhoeven]

Hi John,

On Mon, 18 Aug 2025 at 18:29, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> The RZ/G3E system controller has various registers that control or report
> some properties specific to individual IPs. The regmap is registered as a
> syscon device to allow these IP drivers to access the registers through the
> regmap API.
>
> As other RZ SoCs might have custom read/write callbacks or max-offsets,
> register a custom regmap configuration.
>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> [claudiu.beznea:
>  - do not check the match->data validity in rz_sysc_probe() as it is
>    always valid
>  - dinamically allocate regmap_cfg]
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thanks for the update!

> v7: As this is a duplicate of [2], address comment received there, that is,
>     use kzalloc() + kfree() for regmap_cfg.

You use __free() instead of kfree()...

> --- a/drivers/soc/renesas/rz-sysc.c
> +++ b/drivers/soc/renesas/rz-sysc.c
> @@ -6,8 +6,10 @@
>   */
>

... so you need to include <linux/cleanup.h>

>  #include <linux/io.h>
> +#include <linux/mfd/syscon.h>
>  #include <linux/of.h>
>  #include <linux/platform_device.h>
> +#include <linux/regmap.h>
>  #include <linux/sys_soc.h>
>
>  #include "rz-sysc.h"

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.18 with the above fixed.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v7 2/6] dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit

[John Madieu]

The Renesas RZ/G3E SoC includes a Thermal Sensor Unit (TSU) block designed
to measure the junction temperature. The device provides real-time
temperature measurements for thermal management, utilizing a single
dedicated channel (channel 1) for temperature sensing.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---

Changes:

v1 -> v2:
 * Fixes reg property specifier to get rid of yamlint warnings
 * Fixes IRQ name to reflect TSU expectations

v2 -> v3:
 * Removees useless 'renesas,tsu-operating-mode' property 

v3 -> v4:
 * Fixes commit message
 * Fixes interrupt description
 * Removes trip point definition

v5: no changes
v6: no changes
v7: Adds documentation for 'renesas,tsu-trim' and removes Rb tag from Krzysztof
    due to this change

 .../thermal/renesas,r9a09g047-tsu.yaml        | 87 +++++++++++++++++++
 1 file changed, 87 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml

diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
new file mode 100644
index 000000000000..70d2af6fcd78
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/renesas,r9a09g047-tsu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G3E Temperature Sensor Unit (TSU)
+
+maintainers:
+  - John Madieu <john.madieu.xa@bp.renesas.com>
+
+description:
+  The Temperature Sensor Unit (TSU) is an integrated thermal sensor that
+  monitors the chip temperature on the Renesas RZ/G3E SoC. The TSU provides
+  real-time temperature measurements for thermal management.
+
+properties:
+  compatible:
+    const: renesas,r9a09g047-tsu
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Conversion complete interrupt signal (pulse)
+      - description: Comparison result interrupt signal (level)
+
+  interrupt-names:
+    items:
+      - const: adi
+      - const: adcmpi
+
+  "#thermal-sensor-cells":
+    const: 0
+
+  renesas,tsu-trim:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle to system controller
+          - description: offset of trim registers
+    description: |
+      Phandle and offset to the system controller containing the TSU
+      calibration trim values. The offset points to the first trim
+      register (OTPTSU1TRMVAL0), with the second trim register
+      (OTPTSU1TRMVAL1) located at offset + 4.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+  - power-domains
+  - interrupts
+  - interrupt-names
+  - "#thermal-sensor-cells"
+  - renesas,tsu-trim
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    tsu: thermal@14002000 {
+        compatible = "renesas,r9a09g047-tsu";
+        reg = <0x14002000 0x1000>;
+        clocks = <&cpg CPG_MOD 0x10a>;
+        resets = <&cpg 0xf8>;
+        power-domains = <&cpg>;
+        interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "adi", "adcmpi";
+        #thermal-sensor-cells = <0>;
+        renesas,tsu-trim = <&sys 0x330>;
+    };
-- 
2.25.1

Re: [PATCH v7 2/6] dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit

[Rob Herring]

On Mon, Aug 18, 2025 at 06:28:48PM +0200, John Madieu wrote:
> The Renesas RZ/G3E SoC includes a Thermal Sensor Unit (TSU) block designed
> to measure the junction temperature. The device provides real-time
> temperature measurements for thermal management, utilizing a single
> dedicated channel (channel 1) for temperature sensing.
> 
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
> 
> Changes:
> 
> v1 -> v2:
>  * Fixes reg property specifier to get rid of yamlint warnings
>  * Fixes IRQ name to reflect TSU expectations
> 
> v2 -> v3:
>  * Removees useless 'renesas,tsu-operating-mode' property 
> 
> v3 -> v4:
>  * Fixes commit message
>  * Fixes interrupt description
>  * Removes trip point definition
> 
> v5: no changes
> v6: no changes
> v7: Adds documentation for 'renesas,tsu-trim' and removes Rb tag from Krzysztof
>     due to this change
> 
>  .../thermal/renesas,r9a09g047-tsu.yaml        | 87 +++++++++++++++++++
>  1 file changed, 87 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
> 
> diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
> new file mode 100644
> index 000000000000..70d2af6fcd78
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
> @@ -0,0 +1,87 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/thermal/renesas,r9a09g047-tsu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G3E Temperature Sensor Unit (TSU)
> +
> +maintainers:
> +  - John Madieu <john.madieu.xa@bp.renesas.com>
> +
> +description:
> +  The Temperature Sensor Unit (TSU) is an integrated thermal sensor that
> +  monitors the chip temperature on the Renesas RZ/G3E SoC. The TSU provides
> +  real-time temperature measurements for thermal management.
> +
> +properties:
> +  compatible:
> +    const: renesas,r9a09g047-tsu
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  interrupts:
> +    items:
> +      - description: Conversion complete interrupt signal (pulse)
> +      - description: Comparison result interrupt signal (level)
> +
> +  interrupt-names:
> +    items:
> +      - const: adi
> +      - const: adcmpi
> +
> +  "#thermal-sensor-cells":
> +    const: 0
> +
> +  renesas,tsu-trim:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      - items:
> +          - description: phandle to system controller
> +          - description: offset of trim registers
> +    description: |

Don't need '|' and wrap at 80 char.

> +      Phandle and offset to the system controller containing the TSU
> +      calibration trim values. The offset points to the first trim
> +      register (OTPTSU1TRMVAL0), with the second trim register
> +      (OTPTSU1TRMVAL1) located at offset + 4.
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - resets
> +  - power-domains
> +  - interrupts
> +  - interrupt-names
> +  - "#thermal-sensor-cells"
> +  - renesas,tsu-trim
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    tsu: thermal@14002000 {

Drop unused labels.

The prefered node name is 'thermal-sensor'.

With those,

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH v7 3/6] thermal: renesas: rzg3e: Add thermal driver for the Renesas RZ/G3E SoC

[John Madieu]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=a, Size: 18970 bytes --]

The RZ/G3E SoC integrates a Temperature Sensor Unit (TSU) block designed
to monitor the chip's junction temperature. This sensor is connected to
channel 1 of the APB port clock/reset and provides temperature measurements.

It also requires calibration values stored in the system controller registers
for accurate temperature measurement. Add a driver for the Renesas RZ/G3E TSU.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---

Changes:

v1 -> v2: fixes IRQ names
v2 -> v3: no changes
v3 -> v4: no changes
v5: Removed curly braces arround single-line protected scoped guards
v6: Clarified comments in driver
v7: Refactored driver structure:
  - removes splinlock usage
  - updates polling timeout as per the datasheet
  - uses average mode to be more accurate
  - uses polling (faster than irq mode) for get_temp() while keeping IRQ for hw
  trip-point cross detection.
  - adds both runtime and sleep PM support

 MAINTAINERS                             |   7 +
 drivers/thermal/renesas/Kconfig         |   7 +
 drivers/thermal/renesas/Makefile        |   1 +
 drivers/thermal/renesas/rzg3e_thermal.c | 574 ++++++++++++++++++++++++
 4 files changed, 589 insertions(+)
 create mode 100644 drivers/thermal/renesas/rzg3e_thermal.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 10614ca41ed0..5480412f556d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21544,6 +21544,13 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/iio/potentiometer/renesas,x9250.yaml
 F:	drivers/iio/potentiometer/x9250.c
 
+RENESAS RZ/G3E THERMAL SENSOR UNIT DRIVER
+M:	John Madieu <john.madieu.xa@bp.renesas.com>
+L:	linux-pm@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
+F:	drivers/thermal/renesas/rzg3e_thermal.c
+
 RESET CONTROLLER FRAMEWORK
 M:	Philipp Zabel <p.zabel@pengutronix.de>
 S:	Maintained
diff --git a/drivers/thermal/renesas/Kconfig b/drivers/thermal/renesas/Kconfig
index dcf5fc5ae08e..10cf90fc4bfa 100644
--- a/drivers/thermal/renesas/Kconfig
+++ b/drivers/thermal/renesas/Kconfig
@@ -26,3 +26,10 @@ config RZG2L_THERMAL
 	help
 	  Enable this to plug the RZ/G2L thermal sensor driver into the Linux
 	  thermal framework.
+
+config RZG3E_THERMAL
+	tristate "Renesas RZ/G3E thermal driver"
+	depends on ARCH_RENESAS || COMPILE_TEST
+	help
+	  Enable this to plug the RZ/G3E thermal sensor driver into the Linux
+	  thermal framework.
diff --git a/drivers/thermal/renesas/Makefile b/drivers/thermal/renesas/Makefile
index bf9cb3cb94d6..5a3eba0dedd0 100644
--- a/drivers/thermal/renesas/Makefile
+++ b/drivers/thermal/renesas/Makefile
@@ -3,3 +3,4 @@
 obj-$(CONFIG_RCAR_GEN3_THERMAL)	+= rcar_gen3_thermal.o
 obj-$(CONFIG_RCAR_THERMAL)	+= rcar_thermal.o
 obj-$(CONFIG_RZG2L_THERMAL)	+= rzg2l_thermal.o
+obj-$(CONFIG_RZG3E_THERMAL)	+= rzg3e_thermal.o
diff --git a/drivers/thermal/renesas/rzg3e_thermal.c b/drivers/thermal/renesas/rzg3e_thermal.c
new file mode 100644
index 000000000000..c90791f82f33
--- /dev/null
+++ b/drivers/thermal/renesas/rzg3e_thermal.c
@@ -0,0 +1,574 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G3E TSU Temperature Sensor Unit
+ *
+ * Copyright (C) 2025 Renesas Electronics Corporation
+ */
+#include <linux/clk.h>
+#include <linux/cleanup.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/thermal.h>
+#include <linux/units.h>
+
+#include "../thermal_hwmon.h"
+
+/* TSU Register offsets and bits */
+#define TSU_SSUSR		0x00
+#define TSU_SSUSR_EN_TS		BIT(0)
+#define TSU_SSUSR_ADC_PD_TS	BIT(1)
+#define TSU_SSUSR_SOC_TS_EN	BIT(2)
+
+#define TSU_STRGR		0x04
+#define TSU_STRGR_ADST		BIT(0)
+
+#define TSU_SOSR1		0x08
+#define TSU_SOSR1_ADCT_8	0x03
+#define TSU_SOSR1_ADCS		BIT(3)
+#define TSU_SOSR1_OUTSEL	BIT(9)
+
+#define TSU_SCRR		0x10
+#define TSU_SCRR_OUT12BIT_TS	GENMASK(11, 0)
+
+#define TSU_SSR			0x14
+#define TSU_SSR_CONV		BIT(0)
+
+#define TSU_CMSR		0x18
+#define TSU_CMSR_CMPEN		BIT(0)
+
+#define TSU_LLSR		0x1C
+#define TSU_ULSR		0x20
+
+#define TSU_SISR		0x30
+#define TSU_SISR_ADF		BIT(0)
+#define TSU_SISR_CMPF		BIT(1)
+
+#define TSU_SIER		0x34
+#define TSU_SIER_CMPIE		BIT(1)
+
+#define TSU_SICR		0x38
+#define TSU_SICR_ADCLR		BIT(0)
+#define TSU_SICR_CMPCLR	BIT(1)
+
+/* Temperature calculation constants from datasheet */
+#define TSU_TEMP_D		(-41)
+#define TSU_TEMP_E		126
+#define TSU_CODE_MAX		0xFFF
+
+/* Timing specifications from datasheet */
+#define TSU_POWERUP_TIME_US	120	/* 120T at 1MHz sensor clock per datasheet */
+#define TSU_CONV_TIME_US	50	/* Per sample conversion time */
+#define TSU_POLL_DELAY_US	10	/* Polling interval */
+#define TSU_MIN_CLOCK_RATE	24000000  /* TSU_PCLK minimum 24MHz */
+
+/* Temperature limits */
+#define TSU_TEMP_MIN_MC	(-40000)
+#define TSU_TEMP_MAX_MC	125000
+
+/**
+ * struct rzg3e_thermal_priv - RZ/G3E TSU private data
+ * @base: TSU register base
+ * @dev: device pointer
+ * @syscon: regmap for calibration values
+ * @zone: thermal zone device
+ * @rstc: reset control
+ * @trmval0: calibration value 0 (b)
+ * @trmval1: calibration value 1 (c)
+ * @trim_offset: offset for trim registers in syscon
+ * @lock: protects hardware access during conversions
+ */
+struct rzg3e_thermal_priv {
+	void __iomem *base;
+	struct device *dev;
+	struct regmap *syscon;
+	struct thermal_zone_device *zone;
+	struct reset_control *rstc;
+	u16 trmval0;
+	u16 trmval1;
+	u32 trim_offset;
+	struct mutex lock;
+};
+
+static inline u32 rzg3e_thermal_read(struct rzg3e_thermal_priv *priv, u32 reg)
+{
+	return readl(priv->base + reg);
+}
+
+static inline void rzg3e_thermal_write(struct rzg3e_thermal_priv *priv,
+				       u32 reg, u32 val)
+{
+	writel(val, priv->base + reg);
+}
+
+static int rzg3e_thermal_power_on(struct rzg3e_thermal_priv *priv)
+{
+	u32 val;
+	int ret;
+
+	/* Clear any pending interrupts */
+	rzg3e_thermal_write(priv, TSU_SICR, TSU_SICR_ADCLR | TSU_SICR_CMPCLR);
+
+	/* Disable all interrupts during setup */
+	rzg3e_thermal_write(priv, TSU_SIER, 0);
+
+	/*
+	 * Power-on sequence per datasheet 7.11.9.1:
+	 * SOC_TS_EN must be set at same time or before EN_TS and ADC_PD_TS
+	 */
+	val = TSU_SSUSR_SOC_TS_EN | TSU_SSUSR_EN_TS;
+	rzg3e_thermal_write(priv, TSU_SSUSR, val);
+
+	/* Wait for sensor stabilization per datasheet 7.11.7.1 */
+	usleep_range(TSU_POWERUP_TIME_US, TSU_POWERUP_TIME_US + 10);
+
+	/* Configure for average mode with 8 samples */
+	val = TSU_SOSR1_OUTSEL | TSU_SOSR1_ADCT_8;
+	rzg3e_thermal_write(priv, TSU_SOSR1, val);
+
+	/* Ensure we're in single scan mode (default) */
+	val = rzg3e_thermal_read(priv, TSU_SOSR1);
+	if (val & TSU_SOSR1_ADCS) {
+		dev_err(priv->dev, "Invalid scan mode setting\n");
+		return -EINVAL;
+	}
+
+	/* Wait for any ongoing conversion to complete */
+	ret = readl_poll_timeout(priv->base + TSU_SSR, val,
+				 !(val & TSU_SSR_CONV),
+				 TSU_POLL_DELAY_US,
+				 USEC_PER_MSEC);
+	if (ret) {
+		dev_err(priv->dev, "Timeout waiting for conversion\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void rzg3e_thermal_power_off(struct rzg3e_thermal_priv *priv)
+{
+	/* Disable all interrupts */
+	rzg3e_thermal_write(priv, TSU_SIER, 0);
+
+	/* Clear pending interrupts */
+	rzg3e_thermal_write(priv, TSU_SICR, TSU_SICR_ADCLR | TSU_SICR_CMPCLR);
+
+	/* Power down sequence per datasheet */
+	rzg3e_thermal_write(priv, TSU_SSUSR, TSU_SSUSR_ADC_PD_TS);
+}
+
+/*
+ * Convert 12-bit sensor code to temperature in millicelsius
+ * Formula from datasheet 7.11.7.8:
+ * T(°C) = ((e - d) / (c - b)) * (a - b) + d
+ * where: a = sensor code, b = trmval0, c = trmval1, d = -41, e = 126
+ */
+static int rzg3e_thermal_code_to_temp(struct rzg3e_thermal_priv *priv, u16 code)
+{
+	s64 numerator, denominator;
+	int temp_c;
+
+	numerator = (TSU_TEMP_E - TSU_TEMP_D) * (s64)(code - priv->trmval0);
+	denominator = priv->trmval1 - priv->trmval0;
+
+	temp_c = div64_s64(numerator, denominator) + TSU_TEMP_D;
+
+	return clamp(temp_c * MILLIDEGREE_PER_DEGREE,
+		     TSU_TEMP_MIN_MC, TSU_TEMP_MAX_MC);
+}
+
+/*
+ * Convert temperature in millicelsius to 12-bit sensor code
+ * Formula from datasheet 7.11.7.9 (inverse of above)
+ */
+static u16 rzg3e_thermal_temp_to_code(struct rzg3e_thermal_priv *priv, int temp_mc)
+{
+	int temp_c = temp_mc / MILLIDEGREE_PER_DEGREE;
+	s64 numerator, denominator;
+	s64 code;
+
+	numerator = (temp_c - TSU_TEMP_D) * (priv->trmval1 - priv->trmval0);
+	denominator = TSU_TEMP_E - TSU_TEMP_D;
+
+	code = div64_s64(numerator, denominator) + priv->trmval0;
+
+	return clamp_val(code, 0, TSU_CODE_MAX);
+}
+
+static int rzg3e_thermal_get_temp(struct thermal_zone_device *tz, int *temp)
+{
+	struct rzg3e_thermal_priv *priv = thermal_zone_device_priv(tz);
+	u32 status, code;
+	int ret, timeout;
+
+	ret = pm_runtime_resume_and_get(priv->dev);
+	if (ret < 0)
+		return ret;
+
+	guard(mutex)(&priv->lock);
+
+	/* Clear any previous conversion status */
+	rzg3e_thermal_write(priv, TSU_SICR, TSU_SICR_ADCLR);
+
+	/* Start single conversion */
+	rzg3e_thermal_write(priv, TSU_STRGR, TSU_STRGR_ADST);
+
+	/* Wait for conversion completion - 8 samples at ~50us each */
+	timeout = TSU_CONV_TIME_US * 8 * 2;  /* Double for margin */
+	ret = readl_poll_timeout(priv->base + TSU_SISR, status,
+				 status & TSU_SISR_ADF,
+				 TSU_POLL_DELAY_US, timeout);
+	if (ret) {
+		dev_err(priv->dev, "Conversion timeout (status=0x%08x)\n", status);
+		goto out;
+	}
+
+	/* Read the averaged result and clear the complete flag */
+	code = rzg3e_thermal_read(priv, TSU_SCRR) & TSU_SCRR_OUT12BIT_TS;
+	rzg3e_thermal_write(priv, TSU_SICR, TSU_SICR_ADCLR);
+
+	/* Convert to temperature */
+	*temp = rzg3e_thermal_code_to_temp(priv, code);
+
+	dev_dbg(priv->dev, "temp=%d mC (%d.%03d°C), code=0x%03x\n",
+		*temp, *temp / 1000, abs(*temp) % 1000, code);
+
+out:
+	pm_runtime_mark_last_busy(priv->dev);
+	pm_runtime_put_autosuspend(priv->dev);
+	return ret;
+}
+
+static int rzg3e_thermal_set_trips(struct thermal_zone_device *tz,
+				   int low, int high)
+{
+	struct rzg3e_thermal_priv *priv = thermal_zone_device_priv(tz);
+	u16 low_code, high_code;
+	u32 val;
+	int ret;
+
+	/* Hardware requires low < high */
+	if (low >= high)
+		return -EINVAL;
+
+	ret = pm_runtime_resume_and_get(priv->dev);
+	if (ret < 0)
+		return ret;
+
+	guard(mutex)(&priv->lock);
+
+	/* Convert temperatures to codes */
+	low_code = rzg3e_thermal_temp_to_code(priv, low);
+	high_code = rzg3e_thermal_temp_to_code(priv, high);
+
+	dev_dbg(priv->dev, "set_trips: low=%d high=%d (codes: 0x%03x/0x%03x)\n",
+		low, high, low_code, high_code);
+
+	/* Disable comparison during reconfiguration */
+	rzg3e_thermal_write(priv, TSU_SIER, 0);
+	rzg3e_thermal_write(priv, TSU_CMSR, 0);
+
+	/* Clear any pending comparison interrupts */
+	rzg3e_thermal_write(priv, TSU_SICR, TSU_SICR_CMPCLR);
+
+	/* Set trip points */
+	rzg3e_thermal_write(priv, TSU_LLSR, low_code);
+	rzg3e_thermal_write(priv, TSU_ULSR, high_code);
+
+	/*
+	 * Ensure OUTSEL is set for comparison per datasheet 7.11.7.4
+	 * Comparison uses averaged data
+	 */
+	val = rzg3e_thermal_read(priv, TSU_SOSR1);
+	val |= TSU_SOSR1_OUTSEL;
+	rzg3e_thermal_write(priv, TSU_SOSR1, val);
+
+	/* Enable comparison with "out of range" mode (CMPCOND=0) */
+	rzg3e_thermal_write(priv, TSU_CMSR, TSU_CMSR_CMPEN);
+
+	/* Unmask compare IRQ and start a conversion to evaluate window */
+	rzg3e_thermal_write(priv, TSU_SIER, TSU_SIER_CMPIE);
+	rzg3e_thermal_write(priv, TSU_STRGR, TSU_STRGR_ADST);
+
+	pm_runtime_mark_last_busy(priv->dev);
+	pm_runtime_put_autosuspend(priv->dev);
+
+	return 0;
+}
+
+static irqreturn_t rzg3e_thermal_irq_thread(int irq, void *data)
+{
+	struct rzg3e_thermal_priv *priv = data;
+
+	dev_dbg(priv->dev, "Temperature threshold crossed\n");
+
+	/* Notify thermal framework to re-evaluate trip points */
+	thermal_zone_device_update(priv->zone, THERMAL_TRIP_VIOLATED);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t rzg3e_thermal_irq(int irq, void *data)
+{
+	struct rzg3e_thermal_priv *priv = data;
+	u32 status;
+
+	status = rzg3e_thermal_read(priv, TSU_SISR);
+
+	/* Check if comparison interrupt occurred */
+	if (status & TSU_SISR_CMPF) {
+		/* Clear irq flag and disable interrupt until reconfigured */
+		rzg3e_thermal_write(priv, TSU_SICR, TSU_SICR_CMPCLR);
+		rzg3e_thermal_write(priv, TSU_SIER, 0);
+
+		return IRQ_WAKE_THREAD;
+	}
+
+	return IRQ_NONE;
+}
+
+static const struct thermal_zone_device_ops rzg3e_tz_ops = {
+	.get_temp = rzg3e_thermal_get_temp,
+	.set_trips = rzg3e_thermal_set_trips,
+};
+
+static int rzg3e_thermal_get_calibration(struct rzg3e_thermal_priv *priv)
+{
+	u32 val;
+	int ret;
+
+	/* Read calibration values from syscon */
+	ret = regmap_read(priv->syscon, priv->trim_offset, &val);
+	if (ret)
+		return ret;
+	priv->trmval0 = val & GENMASK(11, 0);
+
+	ret = regmap_read(priv->syscon, priv->trim_offset + 4, &val);
+	if (ret)
+		return ret;
+	priv->trmval1 = val & GENMASK(11, 0);
+
+	/* Validate calibration data */
+	if (!priv->trmval0 || !priv->trmval1 ||
+	    priv->trmval0 == priv->trmval1 ||
+	    priv->trmval0 == 0xFFF || priv->trmval1 == 0xFFF) {
+		dev_err(priv->dev, "Invalid calibration: b=0x%03x, c=0x%03x\n",
+			priv->trmval0, priv->trmval1);
+		return -EINVAL;
+	}
+
+	dev_dbg(priv->dev, "Calibration: b=0x%03x (%u), c=0x%03x (%u)\n",
+		priv->trmval0, priv->trmval0, priv->trmval1, priv->trmval1);
+
+	return 0;
+}
+
+static int rzg3e_thermal_parse_dt(struct rzg3e_thermal_priv *priv)
+{
+	struct device_node *np = priv->dev->of_node;
+	struct of_phandle_args args;
+	int ret;
+
+	ret = of_parse_phandle_with_args(np, "renesas,tsu-trim",
+					 "#address-cells", 0, &args);
+	if (ret)
+		return dev_err_probe(priv->dev, ret,
+				     "Failed to parse renesas,tsu-trim\n");
+
+	if (args.args_count < 1) {
+		dev_err(priv->dev, "Invalid renesas,tsu-trim property\n");
+		of_node_put(args.np);
+		return -EINVAL;
+	}
+
+	priv->trim_offset = args.args[0];
+
+	priv->syscon = syscon_node_to_regmap(args.np);
+	of_node_put(args.np);
+
+	if (IS_ERR(priv->syscon))
+		return dev_err_probe(priv->dev, PTR_ERR(priv->syscon),
+				     "Failed to get syscon regmap\n");
+
+	return 0;
+}
+
+static int rzg3e_thermal_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct rzg3e_thermal_priv *priv;
+	struct clk *clk;
+	int irq, ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = dev;
+	mutex_init(&priv->lock);
+	platform_set_drvdata(pdev, priv);
+
+	priv->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	/* Parse device tree for trim register info */
+	ret = rzg3e_thermal_parse_dt(priv);
+	if (ret)
+		return ret;
+
+	/* Get clock to verify frequency - clock is managed by power domain */
+	clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(clk))
+		return dev_err_probe(dev, PTR_ERR(clk),
+				     "Failed to get clock\n");
+
+	if (clk_get_rate(clk) < TSU_MIN_CLOCK_RATE)
+		return dev_err_probe(dev, -EINVAL,
+				     "Clock rate %lu Hz too low (min %u Hz)\n",
+				     clk_get_rate(clk), TSU_MIN_CLOCK_RATE);
+
+	priv->rstc = devm_reset_control_get_exclusive_deasserted(dev, NULL);
+	if (IS_ERR(priv->rstc))
+		return dev_err_probe(dev, PTR_ERR(priv->rstc),
+				     "Failed to get/deassert reset control\n");
+
+	/* Get calibration data */
+	ret = rzg3e_thermal_get_calibration(priv);
+	if (ret)
+		return dev_err_probe(dev, ret,
+				     "Failed to get valid calibration data\n");
+
+	/* Get comparison interrupt */
+	irq = platform_get_irq_byname(pdev, "adcmpi");
+	if (irq < 0)
+		return irq;
+
+	/* Enable runtime PM */
+	pm_runtime_set_autosuspend_delay(dev, 1000);
+	pm_runtime_use_autosuspend(dev);
+	devm_pm_runtime_enable(dev);
+
+	/* Initial hardware setup */
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret < 0)
+		return dev_err_probe(dev, ret, "Runtime resume failed\n");
+
+	/* Register thermal zone - this will trigger DT parsing */
+	priv->zone = devm_thermal_of_zone_register(dev, 0, priv, &rzg3e_tz_ops);
+	if (IS_ERR(priv->zone)) {
+		ret = PTR_ERR(priv->zone);
+		dev_err(dev, "Failed to register thermal zone: %d\n", ret);
+		goto err_pm_put;
+	}
+
+	/* Request threaded IRQ for comparison interrupt */
+	ret = devm_request_threaded_irq(dev, irq, rzg3e_thermal_irq,
+					rzg3e_thermal_irq_thread,
+					IRQF_ONESHOT, "rzg3e_thermal", priv);
+	if (ret) {
+		dev_err(dev, "Failed to request IRQ: %d\n", ret);
+		goto err_pm_put;
+	}
+
+	/* Add hwmon sysfs interface */
+	ret = devm_thermal_add_hwmon_sysfs(dev, priv->zone);
+	if (ret)
+		dev_warn(dev, "Failed to add hwmon sysfs attributes\n");
+
+	pm_runtime_mark_last_busy(dev);
+	pm_runtime_put_autosuspend(dev);
+
+	dev_info(dev, "RZ/G3E thermal sensor registered\n");
+
+	return 0;
+
+err_pm_put:
+	pm_runtime_put_sync(dev);
+	return ret;
+}
+
+static int rzg3e_thermal_runtime_suspend(struct device *dev)
+{
+	struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev);
+
+	rzg3e_thermal_power_off(priv);
+	return 0;
+}
+
+static int rzg3e_thermal_runtime_resume(struct device *dev)
+{
+	struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev);
+
+	return rzg3e_thermal_power_on(priv);
+}
+
+static int rzg3e_thermal_suspend(struct device *dev)
+{
+	struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev);
+
+	/* If device is active, power it off */
+	if (pm_runtime_active(dev))
+		rzg3e_thermal_power_off(priv);
+
+	/* Assert reset to ensure clean state after resume */
+	reset_control_assert(priv->rstc);
+
+	return 0;
+}
+
+static int rzg3e_thermal_resume(struct device *dev)
+{
+	struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev);
+	int ret;
+
+	/* Deassert reset */
+	ret = reset_control_deassert(priv->rstc);
+	if (ret) {
+		dev_err(dev, "Failed to deassert reset: %d\n", ret);
+		return ret;
+	}
+
+	/* If device was active before suspend, power it back on */
+	if (pm_runtime_active(dev))
+		return rzg3e_thermal_power_on(priv);
+
+	return 0;
+}
+
+static const struct dev_pm_ops rzg3e_thermal_pm_ops = {
+	RUNTIME_PM_OPS(rzg3e_thermal_runtime_suspend,
+		       rzg3e_thermal_runtime_resume, NULL)
+	SYSTEM_SLEEP_PM_OPS(rzg3e_thermal_suspend, rzg3e_thermal_resume)
+};
+
+static const struct of_device_id rzg3e_thermal_dt_ids[] = {
+	{ .compatible = "renesas,r9a09g047-tsu" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rzg3e_thermal_dt_ids);
+
+static struct platform_driver rzg3e_thermal_driver = {
+	.driver = {
+		.name = "rzg3e_thermal",
+		.of_match_table = rzg3e_thermal_dt_ids,
+		.pm = pm_ptr(&rzg3e_thermal_pm_ops),
+	},
+	.probe = rzg3e_thermal_probe,
+};
+module_platform_driver(rzg3e_thermal_driver);
+
+MODULE_DESCRIPTION("Renesas RZ/G3E TSU Thermal Sensor Driver");
+MODULE_AUTHOR("John Madieu <john.madieu.xa@bp.renesas.com>");
+MODULE_LICENSE("GPL");
-- 
2.25.1

Re: [PATCH v7 3/6] thermal: renesas: rzg3e: Add thermal driver for the Renesas RZ/G3E SoC

[Geert Uytterhoeven]

Hi John,

On Mon, 18 Aug 2025 at 18:29, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> The RZ/G3E SoC integrates a Temperature Sensor Unit (TSU) block designed
> to monitor the chip's junction temperature. This sensor is connected to
> channel 1 of the APB port clock/reset and provides temperature measurements.
>
> It also requires calibration values stored in the system controller registers
> for accurate temperature measurement. Add a driver for the Renesas RZ/G3E TSU.
>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>

> v7: Refactored driver structure:
>   - removes splinlock usage
>   - updates polling timeout as per the datasheet
>   - uses average mode to be more accurate
>   - uses polling (faster than irq mode) for get_temp() while keeping IRQ for hw
>   trip-point cross detection.
>   - adds both runtime and sleep PM support

Thanks for the update!

I only looked at the code to obtain the trim register offsets.

> --- /dev/null
> +++ b/drivers/thermal/renesas/rzg3e_thermal.c

> +static int rzg3e_thermal_parse_dt(struct rzg3e_thermal_priv *priv)
> +{
> +       struct device_node *np = priv->dev->of_node;
> +       struct of_phandle_args args;
> +       int ret;
> +
> +       ret = of_parse_phandle_with_args(np, "renesas,tsu-trim",
> +                                        "#address-cells", 0, &args);

of_parse_phandle_with_fixed_args(np, "renesas,tsu-trim", 1, 0, &args)

> +       if (ret)
> +               return dev_err_probe(priv->dev, ret,
> +                                    "Failed to parse renesas,tsu-trim\n");
> +
> +       if (args.args_count < 1) {

"!= 1", however, I think this test is no longer needed after moving
to of_parse_phandle_with_fixed_args().

> +               dev_err(priv->dev, "Invalid renesas,tsu-trim property\n");
> +               of_node_put(args.np);
> +               return -EINVAL;
> +       }
> +
> +       priv->trim_offset = args.args[0];
> +
> +       priv->syscon = syscon_node_to_regmap(args.np);
> +       of_node_put(args.np);
> +
> +       if (IS_ERR(priv->syscon))
> +               return dev_err_probe(priv->dev, PTR_ERR(priv->syscon),
> +                                    "Failed to get syscon regmap\n");
> +
> +       return 0;
> +}
Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v7 3/6] thermal: renesas: rzg3e: Add thermal driver for the Renesas RZ/G3E SoC

[John Madieu]

Hi Geert,

Thanks for your feedback!

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Tuesday, August 19, 2025 9:50 AM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH v7 3/6] thermal: renesas: rzg3e: Add thermal driver for
> the Renesas RZ/G3E SoC
> 
> Hi John,
> 
> On Mon, 18 Aug 2025 at 18:29, John Madieu <john.madieu.xa@bp.renesas.com>
> wrote:
> > The RZ/G3E SoC integrates a Temperature Sensor Unit (TSU) block
> > designed to monitor the chip's junction temperature. This sensor is
> > connected to channel 1 of the APB port clock/reset and provides
> temperature measurements.
> >
> > It also requires calibration values stored in the system controller
> > registers for accurate temperature measurement. Add a driver for the
> Renesas RZ/G3E TSU.
> >
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> 
> > v7: Refactored driver structure:
> >   - removes splinlock usage
> >   - updates polling timeout as per the datasheet
> >   - uses average mode to be more accurate
> >   - uses polling (faster than irq mode) for get_temp() while keeping IRQ
> for hw
> >   trip-point cross detection.
> >   - adds both runtime and sleep PM support
> 
> Thanks for the update!
> 
> I only looked at the code to obtain the trim register offsets.
> 
> > --- /dev/null
> > +++ b/drivers/thermal/renesas/rzg3e_thermal.c
> 
> > +static int rzg3e_thermal_parse_dt(struct rzg3e_thermal_priv *priv) {
> > +       struct device_node *np = priv->dev->of_node;
> > +       struct of_phandle_args args;
> > +       int ret;
> > +
> > +       ret = of_parse_phandle_with_args(np, "renesas,tsu-trim",
> > +                                        "#address-cells", 0, &args);
> 
> of_parse_phandle_with_fixed_args(np, "renesas,tsu-trim", 1, 0, &args)
> 
> > +       if (ret)
> > +               return dev_err_probe(priv->dev, ret,
> > +                                    "Failed to parse
> > + renesas,tsu-trim\n");
> > +
> > +       if (args.args_count < 1) {
> 
> "!= 1", however, I think this test is no longer needed after moving to
> of_parse_phandle_with_fixed_args().

Thanks! Will use this fixed_args() variant in next series and remove
adapt the code accordingly.

> 
> > +               dev_err(priv->dev, "Invalid renesas,tsu-trim
> property\n");
> > +               of_node_put(args.np);
> > +               return -EINVAL;
> > +       }
> > +
> > +       priv->trim_offset = args.args[0];
> > +
> > +       priv->syscon = syscon_node_to_regmap(args.np);
> > +       of_node_put(args.np);
> > +
> > +       if (IS_ERR(priv->syscon))
> > +               return dev_err_probe(priv->dev, PTR_ERR(priv->syscon),
> > +                                    "Failed to get syscon regmap\n");
> > +
> > +       return 0;
> > +}
> Gr{oetje,eeting}s,

Regards,
John

> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
>                                 -- Linus Torvalds

[PATCH v7 4/6] arm64: dts: renesas: r9a09g047: Add #address-cells property in sys node

[John Madieu]

A couple of registers of the system controller (sys) are shared with the TSU
device. Add #address-cells property to sys node to allow proper parsing a
access to these registers from the TSU driver.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---

Changes:
 - v7: new patch: as sys specifier has changed for TSU node, add this patch
 to specify #address-cells.

 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index e4fac7e0d764..7cbba492edd5 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -278,6 +278,7 @@ sys: system-controller@10430000 {
 			reg = <0 0x10430000 0 0x10000>;
 			clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>;
 			resets = <&cpg 0x30>;
+			#address-cells = <1>;
 		};
 
 		xspi: spi@11030000 {
-- 
2.25.1

Re: [PATCH v7 4/6] arm64: dts: renesas: r9a09g047: Add #address-cells property in sys node

[Geert Uytterhoeven]

Hi John,

On Mon, 18 Aug 2025 at 18:29, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> A couple of registers of the system controller (sys) are shared with the TSU
> device. Add #address-cells property to sys node to allow proper parsing a
> access to these registers from the TSU driver.
>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> @@ -278,6 +278,7 @@ sys: system-controller@10430000 {
>                         reg = <0 0x10430000 0 0x10000>;
>                         clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>;
>                         resets = <&cpg 0x30>;
> +                       #address-cells = <1>;

Iff you need this, you need to update the DT bindings first, as reported
by Rob's bot.

However, looking at Claudiu's USB series [1], I think you can do
without, by calling of_parse_phandle_with_fixed_args() instead of
of_parse_phandle_with_args() in the driver.

>                 };
>
>                 xspi: spi@11030000 {

[1] "[PATCH v5 0/7] Add initial USB support for the Renesas RZ/G3S SoC"
    https://lore.kernel.org/20250819054212.486426-1-claudiu.beznea.uj@bp.renesas.com

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v7 4/6] arm64: dts: renesas: r9a09g047: Add #address-cells property in sys node

[John Madieu]

Hi Geert,

Thanks for your review!

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Tuesday, August 19, 2025 9:44 AM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH v7 4/6] arm64: dts: renesas: r9a09g047: Add #address-
> cells property in sys node
> 
> Hi John,
> 
> On Mon, 18 Aug 2025 at 18:29, John Madieu <john.madieu.xa@bp.renesas.com>
> wrote:
> > A couple of registers of the system controller (sys) are shared with
> > the TSU device. Add #address-cells property to sys node to allow
> > proper parsing a access to these registers from the TSU driver.
> >
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> > @@ -278,6 +278,7 @@ sys: system-controller@10430000 {
> >                         reg = <0 0x10430000 0 0x10000>;
> >                         clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>;
> >                         resets = <&cpg 0x30>;
> > +                       #address-cells = <1>;
> 
> Iff you need this, you need to update the DT bindings first, as reported by
> Rob's bot.
> 
> However, looking at Claudiu's USB series [1], I think you can do without,
> by calling of_parse_phandle_with_fixed_args() instead of
> of_parse_phandle_with_args() in the driver.
> 
> >                 };

Indeed, I'll use the fixed_args() option and drop this patch
in v8.

> >
> >                 xspi: spi@11030000 {
> 
> [1] "[PATCH v5 0/7] Add initial USB support for the Renesas RZ/G3S SoC"
>     https://lore.kernel.org/20250819054212.486426-1-
> claudiu.beznea.uj@bp.renesas.com
> 
> Gr{oetje,eeting}s,

Regards,
John

> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
>                                 -- Linus Torvalds

[PATCH v7 5/6] arm64: dts: renesas: r9a09g047: Add TSU node

[John Madieu]

Add TSU node along with thermal zones and keep it enabled in the SoC DTSI.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---

Changes:

v1 -> v2: Fix IRQ names
v2 -> v3: remove useless 'renesas,tsu-operating-mode' property'
v3 -> v4: no changes
v5: no changes
v6: no changes
v7: updated both property name and specifier (<phandle offset>) for trim property.

 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 48 ++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 7cbba492edd5..6744e17ae127 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -64,6 +64,7 @@ cpu0: cpu@0 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -74,6 +75,7 @@ cpu1: cpu@100 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -84,6 +86,7 @@ cpu2: cpu@200 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -94,6 +97,7 @@ cpu3: cpu@300 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -413,6 +417,19 @@ wdt3: watchdog@13000400 {
 			status = "disabled";
 		};
 
+		tsu: thermal@14002000 {
+			compatible = "renesas,r9a09g047-tsu";
+			reg = <0 0x14002000 0 0x1000>;
+			interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "adi", "adcmpi";
+			clocks = <&cpg CPG_MOD 0x10a>;
+			resets = <&cpg 0xf8>;
+			power-domains = <&cpg>;
+			#thermal-sensor-cells = <0>;
+			renesas,tsu-trim = <&sys 0x330>;
+		};
+
 		i2c0: i2c@14400400 {
 			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
 			reg = <0 0x14400400 0 0x400>;
@@ -971,6 +988,37 @@ stmmac_axi_setup: stmmac-axi-config {
 		snps,blen = <16 8 4 0 0 0 0>;
 	};
 
+	thermal-zones {
+		cpu-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&tsu>;
+
+			cooling-maps {
+				map0 {
+					trip = <&target>;
+					cooling-device = <&cpu0 0 3>, <&cpu1 0 3>,
+							 <&cpu2 0 3>, <&cpu3 0 3>;
+					contribution = <1024>;
+				};
+			};
+
+			trips {
+				target: trip-point {
+					temperature = <95000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+
+				sensor_crit: sensor-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-- 
2.25.1

[PATCH v7 6/6] arm64: defconfig: Enable the Renesas RZ/G3E thermal driver

[John Madieu]

Enable the Renesas RZ/G3E thermal driver, as used on the Renesas
RZ/G3E SMARC EVK board.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 58f87d09366c..8def47e094d0 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -728,6 +728,7 @@ CONFIG_ROCKCHIP_THERMAL=m
 CONFIG_RCAR_THERMAL=y
 CONFIG_RCAR_GEN3_THERMAL=y
 CONFIG_RZG2L_THERMAL=y
+CONFIG_RZG3E_THERMAL=y
 CONFIG_ARMADA_THERMAL=y
 CONFIG_MTK_THERMAL=m
 CONFIG_MTK_LVTS_THERMAL=m
-- 
2.25.1

Re: [PATCH v7 0/6] thermal: renesas: Add support for RZ/G3E

[Rob Herring (Arm)]

On Mon, 18 Aug 2025 18:28:46 +0200, John Madieu wrote:
> This series adds support for the temperature sensor unit (TSU) found on the
> Renesas RZ/G3E SoC.
> 
> The series consists of 5 patches (one of which is not related to the thermal
> framework) that progressively add TSU support as follows:
> - patch 1/6:    adds syscon/regmap support for accessing system controller
>                 registers, enabling access to TSU calibration values
> 
> - patch 2-6/6:  adds dt-bindings, actual driver, DT node, and config symbol.
> 
> Patch 1/6 has been duplicated at [1] in USB series. This series addresses comments
> got from there.
> 
> Changes:
> 
> v1 -> v2
>  * Fix yaml warnings from dt-binding
>  * Update IRQ names to reflect TSU expectations
> 
> v2 -> v3
>  * Remove useless 'renesas,tsu-operating-mode' property
> 
> v3 -> v4
>  * Improve commit messages
> 
> v4 -> v5
>  * Remove useless curly braces on single line-protected scoped guards
> 
> v5 -> v6
>  * Minor typo fix
>  * Constify regmap config in patch 1/5
> 
> v6 -> v7
>  * Update DTS trim priperty name and specifier, updading the documentation
>  accordingly
>  * Refactor main driver: remove spinlock usage, using polling timeout as computed
>  from datasheet. Also use polling for get_temp() while using IRQ for trip-point
>  cross detection, and finally add both runtime and sleep PM support.
>  * Add new patch to update sys #address-cells as trim specifier now requires an
>  offet from sys base
> 
> Regards,
> 
> [1] https://lore.kernel.org/all/20250808061806.2729274-2-claudiu.beznea.uj@bp.renesas.com/
> 
> 
> John Madieu (6):
>   soc: renesas: rz-sysc: Add syscon/regmap support
>   dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit
>   thermal: renesas: rzg3e: Add thermal driver for the Renesas RZ/G3E SoC
>   arm64: dts: renesas: r9a09g047: Add #address-cells property in sys
>     node
>   arm64: dts: renesas: r9a09g047: Add TSU node
>   arm64: defconfig: Enable the Renesas RZ/G3E thermal driver
> 
>  .../thermal/renesas,r9a09g047-tsu.yaml        |  87 +++
>  MAINTAINERS                                   |   7 +
>  arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |  49 ++
>  arch/arm64/configs/defconfig                  |   1 +
>  drivers/soc/renesas/Kconfig                   |   1 +
>  drivers/soc/renesas/r9a08g045-sysc.c          |   1 +
>  drivers/soc/renesas/r9a09g047-sys.c           |   1 +
>  drivers/soc/renesas/r9a09g057-sys.c           |   1 +
>  drivers/soc/renesas/rz-sysc.c                 |  28 +-
>  drivers/soc/renesas/rz-sysc.h                 |   2 +
>  drivers/thermal/renesas/Kconfig               |   7 +
>  drivers/thermal/renesas/Makefile              |   1 +
>  drivers/thermal/renesas/rzg3e_thermal.c       | 575 ++++++++++++++++++
>  13 files changed, 760 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
>  create mode 100644 drivers/thermal/renesas/rzg3e_thermal.c
> 
> --
> 2.25.1
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: attempting to guess base-commit...
 Base: tags/v6.17-rc1-12-g0a0e0852f3f3 (best guess, 10/11 blobs matched)

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/renesas/' for 20250818162859.9661-1-john.madieu.xa@bp.renesas.com:

arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dtb: system-controller@10430000 (renesas,r9a09g047-sys): '#address-cells' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml#

RE: [PATCH v7 0/6] thermal: renesas: Add support for RZ/G3E

[John Madieu]

Hi Rob,

Thanks for the feedback!

> -----Original Message-----
> From: Rob Herring (Arm) <robh@kernel.org>
> Sent: Monday, August 18, 2025 8:25 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH v7 0/6] thermal: renesas: Add support for RZ/G3E
> 
> 
> On Mon, 18 Aug 2025 18:28:46 +0200, John Madieu wrote:
> > This series adds support for the temperature sensor unit (TSU) found
> > on the Renesas RZ/G3E SoC.
> >
> > The series consists of 5 patches (one of which is not related to the
> > thermal
> > framework) that progressively add TSU support as follows:
> > - patch 1/6:    adds syscon/regmap support for accessing system
> controller
> >                 registers, enabling access to TSU calibration values
> >
> > - patch 2-6/6:  adds dt-bindings, actual driver, DT node, and config
> symbol.
> >
> > Patch 1/6 has been duplicated at [1] in USB series. This series
> > addresses comments got from there.
> >
> > Changes:
> >
> > v1 -> v2
> >  * Fix yaml warnings from dt-binding
> >  * Update IRQ names to reflect TSU expectations
> >
> > v2 -> v3
> >  * Remove useless 'renesas,tsu-operating-mode' property
> >
> > v3 -> v4
> >  * Improve commit messages
> >
> > v4 -> v5
> >  * Remove useless curly braces on single line-protected scoped guards
> >
> > v5 -> v6
> >  * Minor typo fix
> >  * Constify regmap config in patch 1/5
> >
> > v6 -> v7
> >  * Update DTS trim priperty name and specifier, updading the
> > documentation  accordingly
> >  * Refactor main driver: remove spinlock usage, using polling timeout
> > as computed  from datasheet. Also use polling for get_temp() while
> > using IRQ for trip-point  cross detection, and finally add both runtime
> and sleep PM support.
> >  * Add new patch to update sys #address-cells as trim specifier now
> > requires an  offet from sys base
> >
> > Regards,
> >
> > [1]
> > https://lore.kernel.org/all/20250808061806.2729274-2-claudiu.beznea.uj
> > @bp.renesas.com/
> >
> >
> > John Madieu (6):
> >   soc: renesas: rz-sysc: Add syscon/regmap support
> >   dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit
> >   thermal: renesas: rzg3e: Add thermal driver for the Renesas RZ/G3E SoC
> >   arm64: dts: renesas: r9a09g047: Add #address-cells property in sys
> >     node
> >   arm64: dts: renesas: r9a09g047: Add TSU node
> >   arm64: defconfig: Enable the Renesas RZ/G3E thermal driver
> >
> >  .../thermal/renesas,r9a09g047-tsu.yaml        |  87 +++
> >  MAINTAINERS                                   |   7 +
> >  arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |  49 ++
> >  arch/arm64/configs/defconfig                  |   1 +
> >  drivers/soc/renesas/Kconfig                   |   1 +
> >  drivers/soc/renesas/r9a08g045-sysc.c          |   1 +
> >  drivers/soc/renesas/r9a09g047-sys.c           |   1 +
> >  drivers/soc/renesas/r9a09g057-sys.c           |   1 +
> >  drivers/soc/renesas/rz-sysc.c                 |  28 +-
> >  drivers/soc/renesas/rz-sysc.h                 |   2 +
> >  drivers/thermal/renesas/Kconfig               |   7 +
> >  drivers/thermal/renesas/Makefile              |   1 +
> >  drivers/thermal/renesas/rzg3e_thermal.c       | 575 ++++++++++++++++++
> >  13 files changed, 760 insertions(+), 1 deletion(-)  create mode
> > 100644
> > Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
> >  create mode 100644 drivers/thermal/renesas/rzg3e_thermal.c
> >
> > --
> > 2.25.1
> >
> >
> >
> 
> 
> My bot found new DTB warnings on the .dts files added or changed in this
> series.
> 
> Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
> are fixed by another series. Ultimately, it is up to the platform
> maintainer whether these warnings are acceptable or not. No need to reply
> unless the platform maintainer has comments.
> 
> If you already ran DT checks and didn't see these error(s), then make sure
> dt-schema is up to date:
> 
>   pip3 install dtschema --upgrade
> 
> 
> This patch series was applied (using b4) to base:
>  Base: attempting to guess base-commit...
>  Base: tags/v6.17-rc1-12-g0a0e0852f3f3 (best guess, 10/11 blobs matched)
> 
> If this is not the correct base, please add 'base-commit' tag (or use b4
> which does this automatically)
> 
> New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/renesas/'
> for 20250818162859.9661-1-john.madieu.xa@bp.renesas.com:
> 
> arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dtb: system-
> controller@10430000 (renesas,r9a09g047-sys): '#address-cells' does not
> match any of the regexes: '^pinctrl-[0-9]+$'
> 	from schema $id:
> http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml#
> 

Indeed, I modified the sys node adding #address-cells without documenting it.
That patch will be dropped in next series.

Regards,
John

> 
> 
>