From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E50FCA0EEB for ; Wed, 20 Aug 2025 00:20:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:Cc:To:From: Subject:Message-ID:References:Mime-Version:In-Reply-To:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=PqV10pLXwwjj2OAipIDyVAMMO+u2/mFHIv6eR2zAaWM=; b=R6N/RdoOVUqflEVLH4DCIzxihf TlwvwlnSbOv5SDTwVDNxxtPNI17DqrT4MMNaJfEQNLP/oGoEDnh7GbRm8OFAmEpMGxMb2VW0sRAXa jvQrUB/gR/XJAYedA2StcPafCWm0nOHQlRZG1MZiEbEEJLmkyMqRb/FPD0yAHAGsFp5PGmMW6Y6nW Ql9frCXo+Ikh9HKw6sExrf3d9/0/UZs3Fo9+/TfNne6i6V+bWBRxe3CTLkd8KtBZGowM8Skv4rKIT MQR2omnqgM5tn60u1Hc78zGpyHDWQ34oMBjB53EKmOKLesUPp2SgnOS5Zy0V7ETyOGSnLJNYE5Aua gQYUOU7g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uoWZ9-0000000BwHs-0lRd; Wed, 20 Aug 2025 00:20:35 +0000 Received: from mail-ej1-x649.google.com ([2a00:1450:4864:20::649]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uoUG4-0000000BfVQ-0dT4 for linux-arm-kernel@lists.infradead.org; Tue, 19 Aug 2025 21:52:45 +0000 Received: by mail-ej1-x649.google.com with SMTP id a640c23a62f3a-afcb78e674eso514003066b.1 for ; Tue, 19 Aug 2025 14:52:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1755640362; x=1756245162; darn=lists.infradead.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=PqV10pLXwwjj2OAipIDyVAMMO+u2/mFHIv6eR2zAaWM=; b=QHz/0axIFSM4OrEC2ZI0tNkF/IZEFk2FfwK6RdA19t+DzgKAL8q1lj2wewBuUoQEXG ep0zaX8WNshGeDMAUKQK/zWzjkKOahR783jXbNyGse1xAdnBBaDmRMOJyCUY7QFXaWsE vlx1Sr+M/YH2a/j9fzvqr2OY7EfEw0D4r/VbSuWsgs3DXiAggZ6alpU73FHFQE3W3Ba0 4myZxbRaB9Fp0qT11imxvmJ06cG0OnM/Q28/NSqH9M4ogHXh+GdSs3MDhk/CFhtSmntv rOyS1dKAumZac7O06bv/WIhm12XD8baJ+YD9Ylcn4KZQVRhYmuCIgpyBd21DmO2ARP+m w3HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755640362; x=1756245162; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=PqV10pLXwwjj2OAipIDyVAMMO+u2/mFHIv6eR2zAaWM=; b=KrwlBIsZNXAgw5fl2JrDfGmkfDmlx1tVZ+OkNFGDN3uYnbJ79Js6oN/uRk37nhuCLS c3JwTceUCzpmBWps+QcBs1LjgOpGS9RNznkW0rrLjX+q8/sfS/olqW1By46atzyO0yda EZ00HnMtEMZtH5NqxFrdpxVaLQxClmvdSoLtdKXXeLlQZjTASSK+XLhDDUWAgvYnh+8O Tv3dXqPy3cDtdwkXotSrEompMpwTithgS3IVnB8nwnYhTNp46gTQIjunx8JTF8i32Tl1 NlAmpdsDmfXQGOLpljbhIFeXhoUSbWe1vg+HbPEWEBAIOVJtgsYERWaE5iUJEr3XKOpy /L9Q== X-Forwarded-Encrypted: i=1; AJvYcCWFlAeeFCeU61eZ7NXNxVWDShLlsEzn7NB2Sg+TY19ERaVTf9TVkWY/xSxuAArTRidDEdgEY4oO+2rsD6SpQPH6@lists.infradead.org X-Gm-Message-State: AOJu0YzvhQFseVO+Ph4+7WPK0FYziuLpro9Mw7bV+nCziZf677uX0jr+ xyZeK26WMV1vZ2LoZOpIGsvpOQx8rQGutvEYthPcYVhFZqW90Jiv17bl//ffYPoKM7emySm/bbr 8SKd8DSG4HzHsyw== X-Google-Smtp-Source: AGHT+IGtl/M2mX2DFxMKjU0G/SGsKcUwRPA08PYakKSf6zJpbc9gAmUuIUtlYOT263WzT4l5+3VnMXOmobBQ9w== X-Received: from ejctl25.prod.google.com ([2002:a17:907:c319:b0:ae3:6f1c:e0e1]) (user=smostafa job=prod-delivery.src-stubby-dispatcher) by 2002:a17:907:2d23:b0:ae6:e25b:2413 with SMTP id a640c23a62f3a-afdf0201e20mr32340066b.44.1755640362537; Tue, 19 Aug 2025 14:52:42 -0700 (PDT) Date: Tue, 19 Aug 2025 21:51:47 +0000 In-Reply-To: <20250819215156.2494305-1-smostafa@google.com> Mime-Version: 1.0 References: <20250819215156.2494305-1-smostafa@google.com> X-Mailer: git-send-email 2.51.0.rc1.167.g924127e9c0-goog Message-ID: <20250819215156.2494305-20-smostafa@google.com> Subject: [PATCH v4 19/28] iommu/arm-smmu-v3-kvm: Add MMIO emulation From: Mostafa Saleh To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev Cc: maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, robin.murphy@arm.com, jean-philippe@linaro.org, qperret@google.com, tabba@google.com, jgg@ziepe.ca, mark.rutland@arm.com, praan@google.com, Mostafa Saleh Content-Type: text/plain; charset="UTF-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250819_145244_202520_EDFA4FFE X-CRM114-Status: GOOD ( 19.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org At the moment most registers are just passthrough, then in the next patches CMDQ/STE emulation will be added which inserts logic to some register access. Signed-off-by: Mostafa Saleh --- .../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 125 ++++++++++++++++++ .../iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h | 10 ++ 2 files changed, 135 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c index e45b4e50b1e4..32f199aeec9e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c @@ -8,6 +8,7 @@ #include #include +#include #include "arm_smmu_v3.h" #include "../arm-smmu-v3.h" @@ -140,6 +141,8 @@ static int smmu_init(void) goto out_reclaim_smmu; } + BUILD_BUG_ON(sizeof(hyp_spinlock_t) != sizeof(u32)); + return 0; out_reclaim_smmu: @@ -150,6 +153,127 @@ static int smmu_init(void) return ret; } +static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu, + struct user_pt_regs *regs, + u64 esr, u32 off) +{ + bool is_write = esr & ESR_ELx_WNR; + unsigned int len = BIT((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT); + int rd = (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT; + const u64 read_write = -1ULL; + const u64 no_access = 0; + u64 mask = no_access; + const u64 read_only = is_write ? no_access : read_write; + u64 val = regs->regs[rd]; + + switch (off) { + case ARM_SMMU_IDR0: + /* Clear stage-2 support, hide MSI to avoid write back to cmdq */ + mask = read_only & ~(IDR0_S2P | IDR0_VMID16 | IDR0_MSI | IDR0_HYP); + WARN_ON(len != sizeof(u32)); + break; + /* Passthrough the register access for bisectiblity, handled later */ + case ARM_SMMU_CMDQ_BASE: + case ARM_SMMU_CMDQ_PROD: + case ARM_SMMU_CMDQ_CONS: + case ARM_SMMU_STRTAB_BASE: + case ARM_SMMU_STRTAB_BASE_CFG: + case ARM_SMMU_GBPA: + mask = read_write; + break; + case ARM_SMMU_CR0: + mask = read_write; + WARN_ON(len != sizeof(u32)); + break; + case ARM_SMMU_CR1: { + /* Based on Linux implementation */ + u64 cr2_template = FIELD_PREP(CR1_TABLE_SH, ARM_SMMU_SH_ISH) | + FIELD_PREP(CR1_TABLE_OC, CR1_CACHE_WB) | + FIELD_PREP(CR1_TABLE_IC, CR1_CACHE_WB) | + FIELD_PREP(CR1_QUEUE_SH, ARM_SMMU_SH_ISH) | + FIELD_PREP(CR1_QUEUE_OC, CR1_CACHE_WB) | + FIELD_PREP(CR1_QUEUE_IC, CR1_CACHE_WB); + /* Don't mess with shareability/cacheability. */ + if (is_write) + WARN_ON(val != cr2_template); + mask = read_write; + WARN_ON(len != sizeof(u32)); + break; + } + /* + * These should be safe, just enforce RO or RW and size according to architecture. + * There are some other registers that are not used by Linux as IDR2, IDR4 + * that won't be allowed. + */ + case ARM_SMMU_EVTQ_PROD + SZ_64K: + case ARM_SMMU_EVTQ_CONS + SZ_64K: + case ARM_SMMU_EVTQ_IRQ_CFG1: + case ARM_SMMU_EVTQ_IRQ_CFG2: + case ARM_SMMU_PRIQ_PROD + SZ_64K: + case ARM_SMMU_PRIQ_CONS + SZ_64K: + case ARM_SMMU_PRIQ_IRQ_CFG1: + case ARM_SMMU_PRIQ_IRQ_CFG2: + case ARM_SMMU_GERRORN: + case ARM_SMMU_GERROR_IRQ_CFG1: + case ARM_SMMU_GERROR_IRQ_CFG2: + case ARM_SMMU_IRQ_CTRLACK: + case ARM_SMMU_IRQ_CTRL: + case ARM_SMMU_CR0ACK: + case ARM_SMMU_CR2: + /* These are 32 bit registers. */ + WARN_ON(len != sizeof(u32)); + fallthrough; + case ARM_SMMU_EVTQ_BASE: + case ARM_SMMU_EVTQ_IRQ_CFG0: + case ARM_SMMU_PRIQ_BASE: + case ARM_SMMU_PRIQ_IRQ_CFG0: + case ARM_SMMU_GERROR_IRQ_CFG0: + mask = read_write; + break; + case ARM_SMMU_IIDR: + case ARM_SMMU_IDR5: + case ARM_SMMU_IDR3: + case ARM_SMMU_IDR1: + case ARM_SMMU_GERROR: + WARN_ON(len != sizeof(u32)); + mask = read_only; + }; + + if (WARN_ON(!mask)) + goto out_ret; + + if (is_write) { + if (len == sizeof(u64)) + writeq_relaxed(regs->regs[rd] & mask, smmu->base + off); + else + writel_relaxed(regs->regs[rd] & mask, smmu->base + off); + } else { + if (len == sizeof(u64)) + regs->regs[rd] = readq_relaxed(smmu->base + off) & mask; + else + regs->regs[rd] = readl_relaxed(smmu->base + off) & mask; + } + +out_ret: + return true; +} + +static bool smmu_dabt_handler(struct user_pt_regs *regs, u64 esr, u64 addr) +{ + struct hyp_arm_smmu_v3_device *smmu; + bool ret; + + for_each_smmu(smmu) { + if (addr < smmu->mmio_addr || addr >= smmu->mmio_addr + smmu->mmio_size) + continue; + hyp_spin_lock(&smmu->lock); + ret = smmu_dabt_device(smmu, regs, esr, addr - smmu->mmio_addr); + hyp_spin_unlock(&smmu->lock); + return ret; + } + return false; +} + static void smmu_host_stage2_idmap(phys_addr_t start, phys_addr_t end, int prot) { } @@ -158,4 +282,5 @@ static void smmu_host_stage2_idmap(phys_addr_t start, phys_addr_t end, int prot) struct kvm_iommu_ops smmu_ops = { .init = smmu_init, .host_stage2_idmap = smmu_host_stage2_idmap, + .dabt_handler = smmu_dabt_handler, }; diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h index 3550fa695539..dfeaed728982 100644 --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h @@ -4,6 +4,10 @@ #include +#ifdef __KVM_NVHE_HYPERVISOR__ +#include +#endif + /* * Parameters from the trusted host: * @mmio_addr base address of the SMMU registers @@ -16,6 +20,7 @@ * @oas PA size * @pgsize_bitmap Supported page sizes * @sid_bits Max number of SID bits supported + * @lock Lock to protect SMMU */ struct hyp_arm_smmu_v3_device { phys_addr_t mmio_addr; @@ -26,6 +31,11 @@ struct hyp_arm_smmu_v3_device { unsigned long oas; unsigned long pgsize_bitmap; unsigned int sid_bits; +#ifdef __KVM_NVHE_HYPERVISOR__ + hyp_spinlock_t lock; +#else + u32 lock; +#endif }; extern size_t kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count); -- 2.51.0.rc1.167.g924127e9c0-goog