From: Yicong Yang <yangyicong@huawei.com>
To: <will@kernel.org>, <mark.rutland@arm.com>,
<linux-arm-kernel@lists.infradead.org>
Cc: <sudeep.holla@arm.com>, <james.clark@linaro.org>,
<robh@kernel.org>, <anshuman.khandual@arm.com>,
<jonathan.cameron@huawei.com>, <hejunhao3@huawei.com>,
<linuxarm@huawei.com>, <prime.zeng@hisilicon.com>,
<xuwei5@huawei.com>, <wangyushan12@huawei.com>,
<yangyicong@hisilicon.com>
Subject: [PATCH v2 1/2] perf: arm_pmuv3: Factor out PMCCNTR_EL0 use conditions
Date: Wed, 20 Aug 2025 16:45:33 +0800 [thread overview]
Message-ID: <20250820084534.28037-2-yangyicong@huawei.com> (raw)
In-Reply-To: <20250820084534.28037-1-yangyicong@huawei.com>
From: Yicong Yang <yangyicong@hisilicon.com>
PMCCNTR_EL0 is preferred for counting CPU_CYCLES under certain
conditions. Factor out the condition check to a separate function
for further extension. Add documents for better understanding.
No functional changes intended.
Reviewed-by: James Clark <james.clark@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
---
drivers/perf/arm_pmuv3.c | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c
index f6d7bab5d555..69c5cc8f5606 100644
--- a/drivers/perf/arm_pmuv3.c
+++ b/drivers/perf/arm_pmuv3.c
@@ -978,6 +978,32 @@ static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc,
return -EAGAIN;
}
+static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc,
+ struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
+
+ if (evtype != ARMV8_PMUV3_PERFCTR_CPU_CYCLES)
+ return false;
+
+ /*
+ * A CPU_CYCLES event with threshold counting cannot use PMCCNTR_EL0
+ * since it lacks threshold support.
+ */
+ if (armv8pmu_event_get_threshold(&event->attr))
+ return false;
+
+ /*
+ * PMCCNTR_EL0 is not affected by BRBE controls like BRBCR_ELx.FZP.
+ * So don't use it for branch events.
+ */
+ if (has_branch_stack(event))
+ return false;
+
+ return true;
+}
+
static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
struct perf_event *event)
{
@@ -986,8 +1012,7 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
/* Always prefer to place a cycle counter into the cycle counter. */
- if ((evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) &&
- !armv8pmu_event_get_threshold(&event->attr) && !has_branch_stack(event)) {
+ if (armv8pmu_can_use_pmccntr(cpuc, event)) {
if (!test_and_set_bit(ARMV8_PMU_CYCLE_IDX, cpuc->used_mask))
return ARMV8_PMU_CYCLE_IDX;
else if (armv8pmu_event_is_64bit(event) &&
--
2.24.0
next prev parent reply other threads:[~2025-08-20 9:25 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-20 8:45 [PATCH v2 0/2] perf: arm_pmuv3: Don't use PMCCNTR_EL0 on SMT cores Yicong Yang
2025-08-20 8:45 ` Yicong Yang [this message]
2025-08-20 8:45 ` [PATCH v2 2/2] " Yicong Yang
2025-09-18 13:32 ` Will Deacon
2025-09-19 8:56 ` Yicong Yang
2025-09-19 9:16 ` Mark Rutland
2025-09-19 10:27 ` Yicong Yang
2025-09-19 11:17 ` Will Deacon
2025-09-19 9:37 ` Sudeep Holla
2025-09-19 11:18 ` Will Deacon
2025-09-08 7:09 ` [PATCH v2 0/2] " Yicong Yang
2025-09-18 16:43 ` Will Deacon
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