From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7651DCA0EFA for ; Thu, 21 Aug 2025 22:57:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=cL9PKhJekEhSXNWUDcEOIhh2dmhgVbWzerNgTI7h9Ew=; b=tuOiSbKVKUb+e5nP1izpU8SNGL WqUivnaTVzILA9S4oyZmr5mlUlRmJtR1szbbRVswr7MPktNraSuSkBt+u4wgHUjY4B29fO9yPzOpF Z91Kq3k3K2XrAFlWLuL+8jUTlpIRdwn/2fsohTriDIHzvYpS+r7+W8VdSyS+NIktxyxN4VVOESsTd nMHxIGhoBWwVbjWEmgXNlByEyBSAhyqTYkQvzPefYQ1sC7Efw/3h3quortZu+HKw75JppMbwuffIA ivukgWR+YKdnKaYV/rzswdPEOjJLEG1KwaE5Rn7P1Sk8u3jFStTvHvSNtLPZ/FVrfoviAa0et2H4x SBuer6Mg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1upEE6-00000000sbj-22wa; Thu, 21 Aug 2025 22:57:46 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1up91d-000000003gH-3yDc for linux-arm-kernel@lists.infradead.org; Thu, 21 Aug 2025 17:24:35 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2C4A4152B; Thu, 21 Aug 2025 10:24:25 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D7F023F59E; Thu, 21 Aug 2025 10:24:29 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, anshuman.khandual@arm.com, robh@kernel.org, james.morse@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, Dave.Martin@arm.com, ahmed.genidi@arm.com, kevin.brodsky@arm.com, scott@os.amperecomputing.com, mbenes@suse.cz, james.clark@linaro.org, frederic@kernel.org, rafael@kernel.org, pavel@kernel.org, ryan.roberts@arm.com, suzuki.poulose@arm.com, maz@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvmarm@lists.linux.dev, Yeoreum Yun Subject: [PATCH v4 5/5] arm64: make the per-task SCTLR2_EL1 Date: Thu, 21 Aug 2025 18:24:08 +0100 Message-Id: <20250821172408.2101870-6-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250821172408.2101870-1-yeoreum.yun@arm.com> References: <20250821172408.2101870-1-yeoreum.yun@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250821_102434_021729_47472CC8 X-CRM114-Status: GOOD ( 10.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Some bits in SCTLR2_EL1 that control system behavior can be configured on a per-task basis (e.g., fields related to FEAT_CPA2). To support future use of these fields, SCTLR2_EL1 is maintained per task. On platforms without FEAT_SCTLR2 support, there is no functional change and only minimal performance overhead. Signed-off-by: Yeoreum Yun --- arch/arm64/include/asm/processor.h | 3 +++ arch/arm64/kernel/process.c | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index 61d62bfd5a7b..e066116735c6 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -184,6 +184,7 @@ struct thread_struct { u64 mte_ctrl; #endif u64 sctlr_user; + u64 sctlr2_user; u64 svcr; u64 tpidr2_el0; u64 por_el0; @@ -258,6 +259,8 @@ static inline void task_set_sve_vl_onexec(struct task_struct *task, (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | SCTLR_ELx_ENDA | SCTLR_ELx_ENDB | \ SCTLR_EL1_TCF0_MASK) +#define SCTLR2_USER_MASK (0) + static inline void arch_thread_struct_whitelist(unsigned long *offset, unsigned long *size) { diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 96482a1412c6..e54f192c0629 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -698,6 +698,11 @@ void update_sctlr_el1(u64 sctlr) isb(); } +static void update_sctlr2_el1(u64 sctlr2) +{ + sysreg_clear_set_s(SYS_SCTLR2_EL1, SCTLR2_USER_MASK, sctlr2); +} + /* * Thread switching. */ @@ -737,6 +742,10 @@ struct task_struct *__switch_to(struct task_struct *prev, if (prev->thread.sctlr_user != next->thread.sctlr_user) update_sctlr_el1(next->thread.sctlr_user); + if (alternative_has_cap_unlikely(ARM64_HAS_SCTLR2) && + prev->thread.sctlr2_user != next->thread.sctlr2_user) + update_sctlr2_el1(next->thread.sctlr2_user); + /* the actual thread switch */ last = cpu_switch_to(prev, next); -- LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}