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From: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
To: Yannick Fertre <yannick.fertre@foss.st.com>,
	Philippe Cornu <philippe.cornu@foss.st.com>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Maxime Ripard <mripard@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Rob Herring <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	"Maxime Coquelin" <mcoquelin.stm32@gmail.com>,
	Alexandre Torgue <alexandre.torgue@foss.st.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Christophe Roullier <christophe.roullier@foss.st.com>
Cc: <dri-devel@lists.freedesktop.org>, <devicetree@vger.kernel.org>,
	<linux-stm32@st-md-mailman.stormreply.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Subject: [PATCH v5 08/13] drm/stm: ltdc: handle lvds pixel clock
Date: Fri, 22 Aug 2025 16:34:17 +0200	[thread overview]
Message-ID: <20250822-drm-misc-next-v5-8-9c825e28f733@foss.st.com> (raw)
In-Reply-To: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com>

From: Yannick Fertre <yannick.fertre@foss.st.com>

Handle LVDS pixel clock.

The LTDC operates with multiple clock domains for register access,
requiring all clocks to be provided during read/write operations.  This
imposes a dependency between the LVDS and LTDC to access correctly all
LTDC registers.  And because both IPs' pixel rates must be synchronized,
the LTDC has to handle the LVDS clock.

Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
Acked-by: Yannick Fertre <yannick.fertre@foss.st.com>
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
---
 drivers/gpu/drm/stm/ltdc.c | 22 +++++++++++++++++++++-
 drivers/gpu/drm/stm/ltdc.h |  1 +
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 17548dd3484a0a3e1015c58c752b80f8892a0ff7..f84a9a8590f0653e422798ff61804d7c3966caef 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -837,6 +837,12 @@ ltdc_crtc_mode_valid(struct drm_crtc *crtc,
 	int target_max = target + CLK_TOLERANCE_HZ;
 	int result;
 
+	if (ldev->lvds_clk) {
+		result = clk_round_rate(ldev->lvds_clk, target);
+		drm_dbg_driver(crtc->dev, "lvds pixclk rate target %d, available %d\n",
+			       target, result);
+	}
+
 	result = clk_round_rate(ldev->pixel_clk, target);
 
 	DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
@@ -1878,6 +1884,8 @@ void ltdc_suspend(struct drm_device *ddev)
 	clk_disable_unprepare(ldev->pixel_clk);
 	if (ldev->bus_clk)
 		clk_disable_unprepare(ldev->bus_clk);
+	if (ldev->lvds_clk)
+		clk_disable_unprepare(ldev->lvds_clk);
 }
 
 int ltdc_resume(struct drm_device *ddev)
@@ -1895,8 +1903,16 @@ int ltdc_resume(struct drm_device *ddev)
 
 	if (ldev->bus_clk) {
 		ret = clk_prepare_enable(ldev->bus_clk);
-		if (ret)
+		if (ret) {
 			drm_err(ddev, "failed to enable bus clock (%d)\n", ret);
+			return ret;
+		}
+	}
+
+	if (ldev->lvds_clk) {
+		ret = clk_prepare_enable(ldev->lvds_clk);
+		if (ret)
+			drm_err(ddev, "failed to prepare lvds clock\n");
 	}
 
 	return ret;
@@ -1981,6 +1997,10 @@ int ltdc_load(struct drm_device *ddev)
 		}
 	}
 
+	ldev->lvds_clk = devm_clk_get(dev, "lvds");
+	if (IS_ERR(ldev->lvds_clk))
+		ldev->lvds_clk = NULL;
+
 	rstc = devm_reset_control_get_exclusive(dev, NULL);
 
 	mutex_init(&ldev->err_lock);
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index ddfa8ae61a7ba5dc446fae647562d0ec8e6953e1..17b51a7ce28eee5de6d24ca943ca3b1f48695dfd 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -48,6 +48,7 @@ struct ltdc_device {
 	void __iomem *regs;
 	struct regmap *regmap;
 	struct clk *pixel_clk;	/* lcd pixel clock */
+	struct clk *lvds_clk;	/* lvds pixel clock */
 	struct clk *bus_clk;	/* bus clock */
 	struct mutex err_lock;	/* protecting error_status */
 	struct ltdc_caps caps;

-- 
2.25.1



  parent reply	other threads:[~2025-08-23  6:36 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-22 14:34 [PATCH v5 00/13] Enable display support for STM32MP25 Raphael Gallais-Pou
2025-08-22 14:34 ` [PATCH v5 01/13] dt-bindings: display: st: add two new compatibles to LTDC device Raphael Gallais-Pou
2025-08-24  9:21   ` Krzysztof Kozlowski
2025-08-28 13:51   ` Philippe CORNU
2025-08-22 14:34 ` [PATCH v5 02/13] dt-bindings: display: st,stm32-ltdc: add access-controllers property Raphael Gallais-Pou
2025-08-22 14:34 ` [PATCH v5 03/13] dt-bindings: display: st: add new compatible to LVDS device Raphael Gallais-Pou
2025-08-22 14:34 ` [PATCH v5 04/13] dt-bindings: display: st,stm32mp25-lvds: add access-controllers property Raphael Gallais-Pou
2025-08-22 14:34 ` [PATCH v5 05/13] dt-bindings: display: st,stm32mp25-lvds: add power-domains property Raphael Gallais-Pou
2025-08-22 14:34 ` [PATCH v5 06/13] dt-bindings: arm: stm32: add required #clock-cells property Raphael Gallais-Pou
2025-08-28 15:18   ` Christophe ROULLIER
2025-08-28 15:28     ` Raphael Gallais-Pou
2025-08-22 14:34 ` [PATCH v5 07/13] drm/stm: ltdc: support new hardware version for STM32MP25 SoC Raphael Gallais-Pou
2025-08-28 13:52   ` Philippe CORNU
2025-08-22 14:34 ` Raphael Gallais-Pou [this message]
2025-08-28 13:53   ` [PATCH v5 08/13] drm/stm: ltdc: handle lvds pixel clock Philippe CORNU
2025-08-22 14:34 ` [PATCH v5 09/13] arm64: dts: st: add ltdc support on stm32mp251 Raphael Gallais-Pou
2025-08-22 14:34 ` [PATCH v5 10/13] arm64: dts: st: add ltdc support on stm32mp255 Raphael Gallais-Pou
2025-08-22 14:34 ` [PATCH v5 11/13] arm64: dts: st: add lvds " Raphael Gallais-Pou
2025-08-22 14:34 ` [PATCH v5 12/13] arm64: dts: st: add clock-cells to syscfg node on stm32mp251 Raphael Gallais-Pou
2025-08-22 14:34 ` [PATCH v5 13/13] arm64: dts: st: enable display support on stm32mp257f-ev1 board Raphael Gallais-Pou
2025-08-28 15:27 ` [PATCH v5 00/13] Enable display support for STM32MP25 Philippe CORNU
2025-08-29  7:10   ` Raphael Gallais-Pou

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