[PATCH v1 0/7] Initial Kontron SMARC-sAM67 support

[PATCH v1 0/7] Initial Kontron SMARC-sAM67 support

[Michael Walle]

Now that the PMIC support is there, we can finally, upstream the
support for this board. Besides the usual device tree, this
patchset contains the support for the on-board house keeping MCU. It
make extensive reuse of the drivers for the former SMARC-sAL28
board. Besides different hwmon sensors, all the dt binding patches
will just add a board specific compatible (in addition to the old
sl28 compatible) to make any future board specific quirks possible.

I'm aware that there is a patch [1] which moves the sl28cpld MFD
schema to a different directory. Once that patch is merged, I'll
repost this series. But I already want to get some early feedback.

[1] https://lore.kernel.org/r/20250822075712.27314-2-krzysztof.kozlowski@linaro.org/

Michael Walle (7):
  dt-bindings: arm: ti: Add bindings for Kontron SMARC-sAM67 module
  dt-bindings: mfd: sl28cpld: add sa67mcu compatible
  dt-bindings: hwmon: sl28cpld: add sa67mcu compatible
  dt-bindings: watchdog: add SMARC-sAM67 support
  dt-bindings: nvmem: sl28cpld: add sa67mcu compatible
  hwmon: sl28cpld: add SMARC-sAM67 support
  arm64: dts: ti: Add support for Kontron SMARC-sAM67

 .../devicetree/bindings/arm/ti/k3.yaml        |    1 +
 .../hwmon/kontron,sl28cpld-hwmon.yaml         |    1 +
 .../bindings/mfd/kontron,sl28cpld.yaml        |    7 +-
 .../nvmem/layouts/kontron,sl28-vpd.yaml       |    7 +-
 .../watchdog/kontron,sl28cpld-wdt.yaml        |    7 +-
 arch/arm64/boot/dts/ti/Makefile               |    6 +
 .../dts/ti/k3-am67a-kontron-sa67-base.dts     | 1092 +++++++++++++++++
 .../dts/ti/k3-am67a-kontron-sa67-gbe1.dtso    |   19 +
 .../ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso  |   24 +
 drivers/hwmon/sl28cpld-hwmon.c                |   76 +-
 10 files changed, 1234 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts
 create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso
 create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso

-- 
2.39.5

[PATCH v1 1/7] dt-bindings: arm: ti: Add bindings for Kontron SMARC-sAM67 module

[Michael Walle]

Add devicetree bindings for the AM67 based Kontron SMARC-sAM67
module.

Signed-off-by: Michael Walle <mwalle@kernel.org>
---
 Documentation/devicetree/bindings/arm/ti/k3.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
index e80c653fa438..af41f1541850 100644
--- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
+++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
@@ -181,6 +181,7 @@ properties:
         items:
           - enum:
               - beagle,am67a-beagley-ai
+              - kontron,sa67             # Kontron SMARC-sAM67 board
               - ti,j722s-evm
           - const: ti,j722s
 
-- 
2.39.5

[PATCH v1 2/7] dt-bindings: mfd: sl28cpld: add sa67mcu compatible

[Michael Walle]

The Kontron SMARC-sAM67 module features an on-board house keeping uC.
It's designed to be compatible with the older on-board CPLD used on the
SMARC-sAL28 board. To be prepared for any board specific quirks, add a
specific compatible.

Signed-off-by: Michael Walle <mwalle@kernel.org>
---
 .../devicetree/bindings/mfd/kontron,sl28cpld.yaml          | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mfd/kontron,sl28cpld.yaml b/Documentation/devicetree/bindings/mfd/kontron,sl28cpld.yaml
index 37207a97e06c..400f56d6a231 100644
--- a/Documentation/devicetree/bindings/mfd/kontron,sl28cpld.yaml
+++ b/Documentation/devicetree/bindings/mfd/kontron,sl28cpld.yaml
@@ -16,7 +16,12 @@ description: |
 
 properties:
   compatible:
-    const: kontron,sl28cpld
+    oneOf:
+      - items:
+          - enum:
+              - kontron,sa67mcu
+          - const: kontron,sl28cpld
+      - const: kontron,sl28cpld
 
   reg:
     description:
-- 
2.39.5

[PATCH v1 3/7] dt-bindings: hwmon: sl28cpld: add sa67mcu compatible

[Michael Walle]

The Kontron SMARC-sAM67 module features an on-board house keeping uC.
It is designed to be compatible with the older sl28cpld implementation,
but has different sensors, like voltage and temperature monitoring. Add
a new compatible for that board.

Signed-off-by: Michael Walle <mwalle@kernel.org>
---
 .../devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml        | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml b/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml
index 010333cb25c0..0275803e843c 100644
--- a/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml
+++ b/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml
@@ -17,6 +17,7 @@ properties:
   compatible:
     enum:
       - kontron,sl28cpld-fan
+      - kontron,sa67mcu-hwmon
 
   reg:
     maxItems: 1
-- 
2.39.5

[PATCH v1 4/7] dt-bindings: watchdog: add SMARC-sAM67 support

[Michael Walle]

The SMARC-sAM67 board has an on-board uC which has the same register
interface as the older CPLD implementation on the SMARC-sAL28 board.
Although the MCU emulates the same behavior, be prepared for any quirks
and add a board specific compatible.

Signed-off-by: Michael Walle <mwalle@kernel.org>
---
 .../devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml
index 179272f74de5..b5b624e85468 100644
--- a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml
@@ -18,7 +18,12 @@ allOf:
 
 properties:
   compatible:
-    const: kontron,sl28cpld-wdt
+    oneOf:
+      - items:
+          - enum:
+              - kontron,sa67mcu-wdt
+          - const: kontron,sl28cpld-wdt
+      - const: kontron,sl28cpld-wdt
 
   reg:
     maxItems: 1
-- 
2.39.5

[PATCH v1 5/7] dt-bindings: nvmem: sl28cpld: add sa67mcu compatible

[Michael Walle]

The Kontron SMARC-sAM67 has the same nvmem layout as the SMARC-sAL28. To
To be prepared for any board specific quirks, add a specific compatible.

Signed-off-by: Michael Walle <mwalle@kernel.org>
---
 .../bindings/nvmem/layouts/kontron,sl28-vpd.yaml           | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml b/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml
index c713e23819f1..afd1919c6b1c 100644
--- a/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml
+++ b/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml
@@ -19,7 +19,12 @@ select: false
 
 properties:
   compatible:
-    const: kontron,sl28-vpd
+    oneOf:
+      - items:
+          - enum:
+              - kontron,sa67-vpd
+          - const: kontron,sl28-vpd
+      - const: kontron,sl28-vpd
 
   serial-number:
     type: object
-- 
2.39.5

[PATCH v1 6/7] hwmon: sl28cpld: add SMARC-sAM67 support

[Michael Walle]

The on-board uC on the SMARC-sAM67 board is compatible with the older
CPLD implementation on the SMARC-sAL28 board, but has different sensors,
namely two voltage sensors and one temperature sensor. Add support for it.

Signed-off-by: Michael Walle <mwalle@kernel.org>
---
 drivers/hwmon/sl28cpld-hwmon.c | 76 ++++++++++++++++++++++++++++++++--
 1 file changed, 73 insertions(+), 3 deletions(-)

diff --git a/drivers/hwmon/sl28cpld-hwmon.c b/drivers/hwmon/sl28cpld-hwmon.c
index 454cc844fb9d..670308d9b72f 100644
--- a/drivers/hwmon/sl28cpld-hwmon.c
+++ b/drivers/hwmon/sl28cpld-hwmon.c
@@ -18,6 +18,9 @@
 #define   FAN_SCALE_X8		BIT(7)
 #define   FAN_VALUE_MASK	GENMASK(6, 0)
 
+#define SA67MCU_VOLTAGE(n)	(0x00 + ((n) * 2))
+#define SA67MCU_TEMP(n)		(0x04 + ((n) * 2))
+
 struct sl28cpld_hwmon {
 	struct regmap *regmap;
 	u32 offset;
@@ -75,8 +78,71 @@ static const struct hwmon_chip_info sl28cpld_hwmon_chip_info = {
 	.info = sl28cpld_hwmon_info,
 };
 
+static int sa67mcu_hwmon_read(struct device *dev,
+			      enum hwmon_sensor_types type, u32 attr,
+			      int channel, long *input)
+{
+	struct sl28cpld_hwmon *hwmon = dev_get_drvdata(dev);
+	unsigned int offset;
+	u8 reg[2];
+	int ret;
+
+	switch (type) {
+	case hwmon_in:
+		switch (attr) {
+		case hwmon_in_input:
+			offset = hwmon->offset + SA67MCU_VOLTAGE(channel);
+			break;
+		default:
+			return -EOPNOTSUPP;
+		}
+		break;
+	case hwmon_temp:
+		switch (attr) {
+		case hwmon_temp_input:
+			offset = hwmon->offset + SA67MCU_TEMP(channel);
+			break;
+		default:
+			return -EOPNOTSUPP;
+		}
+		break;
+	default:
+		return -EOPNOTSUPP;
+	}
+
+	/* Reading the low byte will capture the value */
+	ret = regmap_bulk_read(hwmon->regmap, offset, reg, ARRAY_SIZE(reg));
+	if (ret)
+		return ret;
+
+	*input = reg[1] << 8 | reg[0];
+
+	/* Temperatures are s16 and in 0.1degC steps. */
+	if (type == hwmon_temp)
+		*input = sign_extend32(*input, 15) * 100;
+
+	return 0;
+}
+
+static const struct hwmon_channel_info * const sa67mcu_hwmon_info[] = {
+	HWMON_CHANNEL_INFO(in, HWMON_I_INPUT, HWMON_I_INPUT),
+	HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
+	NULL
+};
+
+static const struct hwmon_ops sa67mcu_hwmon_ops = {
+	.visible = 0444,
+	.read = sa67mcu_hwmon_read,
+};
+
+static const struct hwmon_chip_info sa67mcu_hwmon_chip_info = {
+	.ops = &sa67mcu_hwmon_ops,
+	.info = sa67mcu_hwmon_info,
+};
+
 static int sl28cpld_hwmon_probe(struct platform_device *pdev)
 {
+	const struct hwmon_chip_info *chip_info;
 	struct sl28cpld_hwmon *hwmon;
 	struct device *hwmon_dev;
 	int ret;
@@ -84,6 +150,10 @@ static int sl28cpld_hwmon_probe(struct platform_device *pdev)
 	if (!pdev->dev.parent)
 		return -ENODEV;
 
+	chip_info = device_get_match_data(&pdev->dev);
+	if (!chip_info)
+		return -EINVAL;
+
 	hwmon = devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL);
 	if (!hwmon)
 		return -ENOMEM;
@@ -97,8 +167,7 @@ static int sl28cpld_hwmon_probe(struct platform_device *pdev)
 		return -EINVAL;
 
 	hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev,
-				"sl28cpld_hwmon", hwmon,
-				&sl28cpld_hwmon_chip_info, NULL);
+				"sl28cpld_hwmon", hwmon, chip_info, NULL);
 	if (IS_ERR(hwmon_dev))
 		dev_err(&pdev->dev, "failed to register as hwmon device");
 
@@ -106,7 +175,8 @@ static int sl28cpld_hwmon_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id sl28cpld_hwmon_of_match[] = {
-	{ .compatible = "kontron,sl28cpld-fan" },
+	{ .compatible = "kontron,sl28cpld-fan", .data = &sl28cpld_hwmon_chip_info },
+	{ .compatible = "kontron,sa67mcu-hwmon", .data = &sa67mcu_hwmon_chip_info },
 	{}
 };
 MODULE_DEVICE_TABLE(of, sl28cpld_hwmon_of_match);
-- 
2.39.5

[PATCH v1 7/7] arm64: dts: ti: Add support for Kontron SMARC-sAM67

[Michael Walle]

The Kontron SMARC-sAM67 is a SMARC module which features a TI AM67 SoC.
It supports the following features:
 * Quad-core AM67A94 with 1.4GHz
 * 8 GiB RAM
 * 64 GiB eMMC
 * 4 MiB SPI flash for failsafe booting
 * 4x UART
 * 1x USB 2.0
 * 1x USB 3.2 (or 4x USB3.2 with onboard USB 3.2 hub)
 * 1x RTC
 * 2x GBE
 * 1x QSPI (with 2 chip selects)
 * 1x SPI (with 2 chip selects)
 * 7x I2C
 * 4x CSI (*)
 * 2x LVDS (or one dual-link LVDS)
 * 1x DSI (*)
 * 1x DP (*)
 * onboard microcontroller for boot control, failsafe booting and
   external watchdog

(*) not yet supported by the kernel

There is a base device tree and overlays which will add optional
features. At the moment there is one full featured variant of that
board whose device tree is generated during build by merging all the
device tree overlays.

Signed-off-by: Michael Walle <mwalle@kernel.org>
---
 arch/arm64/boot/dts/ti/Makefile               |    6 +
 .../dts/ti/k3-am67a-kontron-sa67-base.dts     | 1092 +++++++++++++++++
 .../dts/ti/k3-am67a-kontron-sa67-gbe1.dtso    |   19 +
 .../ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso  |   24 +
 4 files changed, 1141 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts
 create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso
 create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso

diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index aad9177930e6..7047d3421783 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -133,7 +133,13 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo
 
 # Boards with J722s SoC
+k3-am67a-kontron-sa67-dtbs := k3-am67a-kontron-sa67-base.dtb \
+	k3-am67a-kontron-sa67-rtc-rv8263.dtbo k3-am67a-kontron-sa67-gbe1.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-am67a-beagley-ai.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am67a-kontron-sa67.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am67a-kontron-sa67-base.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am67a-kontron-sa67-gbe1.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-am67a-kontron-sa67-rtc-rv8263.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo
diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts
new file mode 100644
index 000000000000..961d8661ec97
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts
@@ -0,0 +1,1092 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Kontron SMARC-sAM67 module
+ *
+ * Copyright (c) 2025 Kontron Europe GmbH
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include "k3-j722s.dtsi"
+#include "k3-serdes.h"
+
+/ {
+	compatible = "kontron,sa67", "ti,j722s";
+	model = "Kontron SMARC-sAM67";
+
+	aliases {
+		serial0 = &mcu_uart0;
+		serial1 = &main_uart0;
+		serial2 = &main_uart5;
+		serial3 = &wkup_uart0;
+		mmc0 = &sdhci0;
+		mmc1 = &sdhci1;
+		rtc0 = &wkup_rtc0;
+	};
+
+	lcd0_backlight: backlight-1 {
+		compatible = "pwm-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcd0_backlight_pins_default>;
+		pwms = <&epwm1 0 50000 0>;
+		brightness-levels = <0 32 64 96 128 160 192 224 255>;
+		default-brightness-level = <8>;
+		enable-gpios = <&main_gpio0 29 GPIO_ACTIVE_HIGH>;
+		status = "disabled";
+	};
+
+	lcd1_backlight: backlight-2 {
+		compatible = "pwm-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcd1_backlight_pins_default>;
+		pwms = <&epwm1 1 50000 0>;
+		brightness-levels = <0 32 64 96 128 160 192 224 255>;
+		default-brightness-level = <8>;
+		enable-gpios = <&main_gpio1 18 GPIO_ACTIVE_HIGH>;
+		status = "disabled";
+	};
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+
+	connector-1 {
+		compatible = "gpio-usb-b-connector", "usb-b-connector";
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb0_connector_pins_default>;
+		type = "micro";
+		id-gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>;
+		vbus-supply = <&vcc_usb0_vbus>;
+
+		port  {
+			usb0_connector: endpoint {
+				remote-endpoint = <&usb0_hc>;
+			};
+		};
+
+	};
+
+	memory@80000000 {
+		/* Filled in by bootloader */
+		reg = <0x00000000 0x00000000 0x00000000 0x00000000>,
+		      <0x00000000 0x00000000 0x00000000 0x00000000>;
+		device_type = "memory";
+		bootph-pre-ram;
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x10000000>;
+			alignment = <0x2000>;
+			linux,cma-default;
+		};
+
+		secure_tfa_ddr: tfa@9e780000 {
+			reg = <0x00 0x9e780000 0x00 0x80000>;
+			no-map;
+		};
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>;
+			no-map;
+		};
+
+		wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0100000 0x00 0xf00000>;
+			no-map;
+		};
+	};
+
+	vin_5p0: regulator-1 {
+		compatible = "regulator-fixed";
+		regulator-name = "V_3V0_5V25_IN";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+		bootph-all;
+	};
+
+	vcc_3p3_s5: regulator-2 {
+		compatible = "regulator-fixed";
+		regulator-name = "V_3V3_S5";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vin_5p0>;
+		regulator-always-on;
+		regulator-boot-on;
+		bootph-all;
+	};
+
+	vcc_1p8_s5: regulator-3 {
+		compatible = "regulator-fixed";
+		regulator-name = "V_1V8_S5";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vin_5p0>;
+		regulator-always-on;
+		regulator-boot-on;
+		bootph-all;
+	};
+
+	vcc_3p3_s0: regulator-4 {
+		compatible = "regulator-fixed";
+		regulator-name = "V_3V3_S0";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3p3_s5>;
+		regulator-always-on;
+		regulator-boot-on;
+		enable-active-high;
+		gpios = <&tps652g1 1 GPIO_ACTIVE_HIGH>;
+		bootph-all;
+	};
+
+	vcc_3p3_sd_s0: regulator-5 {
+		compatible = "regulator-fixed";
+		regulator-name = "SDIO_PWR_EN";
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_3p3_sd_s0_pins_default>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		enable-active-high;
+		gpios = <&main_gpio0 7 GPIO_ACTIVE_HIGH>;
+		bootph-all;
+	};
+
+	vcc_3p3_sd_vio_s0: regulator-6 {
+		compatible = "regulator-gpio";
+		regulator-name = "V_3V3_1V8_SD_S0";
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_3p3_sd_vio_s0_pins_default>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3p3_s0>;
+		regulator-boot-on;
+		enable-gpios = <&main_gpio0 7 GPIO_ACTIVE_HIGH>;
+		gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>;
+		states = <3300000 0x0>,
+			 <1800000 0x1>;
+		bootph-all;
+	};
+
+	vcc_3p3_cam_s0: regulator-7 {
+		compatible = "regulator-fixed";
+		regulator-name = "V_3V3_CAM_S0";
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_3p3_cam_s0_pins_default>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3p3_s5>;
+		enable-active-high;
+		interrupts-extended = <&main_gpio1 30 IRQ_TYPE_EDGE_FALLING>;
+		bootph-all;
+	};
+
+	vcc_1p1_s0: regulator-8 {
+		compatible = "regulator-fixed";
+		regulator-name = "V_1V1_S0";
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc_1p1_s3>;
+		regulator-always-on;
+		regulator-boot-on;
+		enable-active-high;
+		/* shared with V_0V75_0V85_CORE_S0 */
+		gpios = <&tps652g1 4 GPIO_ACTIVE_HIGH>;
+		bootph-all;
+	};
+
+	vcc_0p85_vcore_s0: regulator-9 {
+		compatible = "regulator-fixed";
+		regulator-name = "V_0V75_0V85_CORE_S0";
+		regulator-min-microvolt = <850000>;
+		regulator-max-microvolt = <850000>;
+		vin-supply = <&vin_5p0>;
+		regulator-always-on;
+		regulator-boot-on;
+		enable-active-high;
+		gpios = <&tps652g1 4 GPIO_ACTIVE_HIGH>;
+		bootph-all;
+	};
+
+	vcc_lcd0_panel: regulator-10 {
+		compatible = "regulator-fixed";
+		regulator-name = "LCD0_VDD_EN";
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_lcd0_panel_pins_default>;
+		enable-active-high;
+		gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>;
+	};
+
+	vcc_lcd1_panel: regulator-11 {
+		compatible = "regulator-fixed";
+		regulator-name = "LCD1_VDD_EN";
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_lcd1_panel_pins_default>;
+		enable-active-high;
+		gpios = <&main_gpio1 19 GPIO_ACTIVE_HIGH>;
+	};
+
+	vcc_usb0_vbus: regulator-12 {
+		compatible = "regulator-fixed";
+		regulator-name = "USB0_EN_OC#";
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_usb0_vbus_pins_default>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpios = <&main_gpio1 50 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&audio_refclk0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&audio_refclk0_pins_default>;
+	status = "disabled";
+};
+
+&audio_refclk1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&audio_refclk1_pins_default>;
+	status = "disabled";
+};
+
+&cpsw3g {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpsw3g_pins_default>, <&rgmii1_pins_default>,
+		    <&rgmii2_pins_default>;
+	status = "okay";
+};
+
+&cpsw3g_mdio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpsw3g_mdio_pins_default>;
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
+&cpsw_port1 {
+	phy-connection-type = "rgmii-id";
+	phy-handle = <&phy0>;
+	nvmem-cells = <&base_mac_address 0>;
+	nvmem-cell-names = "mac-address";
+	status = "okay";
+};
+
+&main_gpio0 {
+	gpio-line-names =
+		"", "", "", "", "", "", "", "SOC_SDIO_PWR_EN", "VSD_SEL",
+		"RESET_OUT#", "I2C_MUX_RST#", "SPI_FLASH_CS#", "QPSI_CS0#",
+		"QSPI_CS1#", "BOOT_SEL1", "BRDCFG0", "BRDCFG1", "BRDCFG2",
+		"BRDCFG3", "BRDCFG4", "", "BRDREV0", "BRDREV1", "", "", "", "",
+		"", "", "LCD0_BKLT_EN", "LCD0_VDD_EN", "GBE_INT#", "DSI0_TE",
+		"CHARGING#", "USB0_OTG_ID", "PMIC_INT#", "RTC_INT#",
+		"EDP_BRIDGE_EN", "EDP_BRIDGE_IRQ#", "", "CHARGER_PRSNT#", "",
+		"", "", "", "BOOT_SEL2#", "CAM2_RST#", "CAM2_PWR#", "",
+		"CAM3_RST#", "CAM3_PWR#", "GPIO0", "GPIO1", "", "", "", "", "",
+		"", "", "", "", "", "", "", "", "", "", "", "GPIO10", "GPIO11",
+		"SLEEP#", "LID#";
+
+	bootph-all;
+	status = "okay";
+};
+
+&main_gpio1 {
+	gpio-line-names =
+		"", "", "", "", "", "", "", "GPIO6", "GPIO7", "", "", "", "",
+		"GPIO8", "GPIO9", "PCIE_A_RST#", "", "BATLOW#", "LCD1_BKLT_EN",
+		"LCD1_VDD_EN", "", "", "", "", "GPIO2", "GPIO3", "", "",
+		"GPIO4", "GPIO5", "CAM_S0_FAULT#", "BOOT_SEL0#", "", "", "", "",
+		"", "", "", "", "", "", "", "", "", "", "", "", "SDIO_CD#", "",
+		"USB0_DRVVBUS", "USB1_DRVVBUS";
+
+	bootph-all;
+	status = "okay";
+};
+
+/* I2C_LOCAL */
+&main_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c0_pins_default>;
+	clock-frequency = <100000>;
+	status = "okay";
+	bootph-all;
+
+	tps652g1: pmic@44 {
+		compatible = "ti,tps652g1";
+		reg = <0x44>;
+		ti,primary-pmic;
+		system-power-controller;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names =
+			"LPM_EN#", "EN_3V3_S0", "POWER_BTN#", "CARRIER_STBY#",
+			"EN_0V75_0V85_VCORE_S0", "PMIC_WAKEUP";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_irq_pins_default>;
+		interrupts-extended = <&main_gpio0 35 IRQ_TYPE_EDGE_FALLING>;
+
+		buck1-supply = <&vin_5p0>;
+		buck2-supply = <&vin_5p0>;
+		buck3-supply = <&vin_5p0>;
+		buck4-supply = <&vin_5p0>;
+		ldo1-supply = <&vin_5p0>;
+		ldo2-supply = <&vin_5p0>;
+		ldo3-supply = <&vin_5p0>;
+
+		bootph-all;
+
+		regulators {
+			vcc_0p85_s0: buck1 {
+				regulator-name = "V_0V85_S0";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vcc_1p1_s3: buck2 {
+				regulator-name = "V_1V1_S3";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vcc_1p8_s0: buck3 {
+				regulator-name = "V_1V8_S0";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vcc_1p2_s0: buck4 {
+				regulator-name = "V_1V2_S0";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vcc_1p8_vda_pll_s0: ldo1 {
+				regulator-name = "V_1V8_VDA_PLL_S0";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vcc_1p8_s3: ldo2 {
+				regulator-name = "V_1V8_S3";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vcc_1p8_ret_s5: ldo3 {
+				regulator-name = "V_1V8_RET_S5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+
+	system-controller@4a {
+		compatible = "kontron,sa67mcu", "kontron,sl28cpld";
+		reg = <0x4a>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		watchdog@4 {
+			compatible = "kontron,sl28cpld-wdt";
+			reg = <0x4>;
+			kontron,assert-wdt-timeout-pin;
+		};
+
+		hwmon@8{
+			compatible = "kontron,sa67mcu-hwmon";
+			reg = <0x8>;
+		};
+	};
+
+	rtc: rtc@51 {
+		compatible = "microcrystal,rv8263";
+		reg = <0x51>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtc_pins_default>;
+		interrupts-extended = <&main_gpio0 36 IRQ_TYPE_EDGE_FALLING>;
+	};
+};
+
+/* I2C_CAM */
+&main_i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c2_pins_default>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9546";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c_mux_pins_default>;
+
+		vdd-supply = <&vcc_1p8_s0>;
+		reset-gpios = <&main_gpio0 10 GPIO_ACTIVE_LOW>;
+
+		i2c_cam0: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+		};
+
+		i2c_cam1: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+		};
+
+		i2c_cam2: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+		};
+
+		i2c_cam3: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+		};
+	};
+};
+
+/* I2C_LCD */
+&main_i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c3_pins_default>;
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&main_pmx0 {
+	audio_refclk0_pins_default: audio-refclk0-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x0c4, PIN_OUTPUT, 5)	/* (W23) VOUT0_DATA3.AUDIO_EXT_REFCLK0 */
+		>;
+	};
+
+	audio_refclk1_pins_default: audio-refclk1-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x0a0, PIN_OUTPUT, 1)	/* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */
+		>;
+	};
+
+	cpsw3g_mdio_pins_default: cpsw3g-mdio-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x160, PIN_OUTPUT, 0)	/* (AC24) MDIO0_MDC */
+			J722S_IOPAD(0x15c, PIN_INPUT, 0)	/* (AD25) MDIO0_MDIO */
+		>;
+	};
+
+	cpsw3g_pins_default: cpsw3g-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x1b8, PIN_OUTPUT, 1)	/* (C20) SPI0_CS1.CP_GEMAC_CPTS0_TS_COMP */
+		>;
+	};
+
+	edp_bridge_pins_default: edp-bridge-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x098, PIN_OUTPUT, 7)	/* (V21) GPMC0_WAIT0.GPIO0_37 */
+			J722S_IOPAD(0x09c, PIN_INPUT, 7)	/* (W26) GPMC0_WAIT1.GPIO0_38 */
+		>;
+	};
+
+	i2c_mux_pins_default: i2c-mux-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x028, PIN_OUTPUT, 7)	/* (M27) OSPI0_D7.GPIO0_10 */
+		>;
+	};
+
+	lcd0_backlight_pins_default: lcd0-backlight-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x074, PIN_OUTPUT, 7)	/* (V22) GPMC0_AD14.GPIO0_29 */
+			J722S_IOPAD(0x110, PIN_OUTPUT, 4)	/* (G27) MMC2_DAT1.EHRPWM1_A */
+		>;
+	};
+
+	lcd1_backlight_pins_default: lcd1-backlight-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x1c0, PIN_OUTPUT, 7)	/* (E19) SPI0_D0.GPIO1_18 */
+			J722S_IOPAD(0x114, PIN_OUTPUT, 4)	/* (G26) MMC2_DAT0.EHRPWM1_B */
+		>;
+	};
+
+	main_i2c0_pins_default: main-i2c0-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x1e0, PIN_INPUT, 0)	/* (D23) I2C0_SCL */
+			J722S_IOPAD(0x1e4, PIN_INPUT, 0)	/* (B22) I2C0_SDA */
+		>;
+		bootph-all;
+	};
+
+	main_i2c2_pins_default: main-i2c2-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x0b0, PIN_INPUT, 1)	/* (P22) GPMC0_CSn2.I2C2_SCL */
+			J722S_IOPAD(0x0b4, PIN_INPUT, 1)	/* (P23) GPMC0_CSn3.I2C2_SDA */
+		>;
+	};
+
+	main_i2c3_pins_default: main-i2c3-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x1d0, PIN_INPUT, 2)	/* (E22) UART0_CTSn.I2C3_SCL */
+			J722S_IOPAD(0x1d4, PIN_INPUT, 2)	/* (B21) UART0_RTSn.I2C3_SDA */
+		>;
+	};
+
+	main_i2c4_pins_default: main-i2c4-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x0a8, PIN_INPUT, 1)	/* (R27) GPMC0_CSn0.I2C4_SCL */
+			J722S_IOPAD(0x0ac, PIN_INPUT, 1)	/* (P21) GPMC0_CSn1.I2C4_SDA */
+		>;
+	};
+
+	main_uart0_pins_default: main-uart0-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x1c8, PIN_INPUT, 0)	/* (F19) UART0_RXD */
+			J722S_IOPAD(0x1cc, PIN_OUTPUT, 0)	/* (F20) UART0_TXD */
+		>;
+		bootph-all;
+	};
+
+	main_uart5_pins_default: main-uart5-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x108, PIN_INPUT, 3)	/* (J27) MMC2_DAT3.UART5_RXD */
+			J722S_IOPAD(0x10c, PIN_OUTPUT, 3)	/* (H27) MMC2_DAT2.UART5_TXD */
+			J722S_IOPAD(0x008, PIN_INPUT, 5)	/* (L22) OSPI0_DQS.UART5_CTSn */
+			J722S_IOPAD(0x004, PIN_OUTPUT, 5)	/* (L23) OSPI0_LBCLKO.UART5_RTSn */
+		>;
+	};
+
+	mcasp0_pins_default: mcasp0-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x1a4, PIN_INPUT, 0)	/* (D25) MCASP0_ACLKX */
+			J722S_IOPAD(0x1a8, PIN_INPUT, 0)	/* (C26) MCASP0_AFSX */
+			J722S_IOPAD(0x1a0, PIN_INPUT, 0)	/* (F23) MCASP0_AXR0 */
+			J722S_IOPAD(0x19c, PIN_OUTPUT, 0)	/* (B25) MCASP0_AXR1 */
+		>;
+	};
+
+	mcasp2_pins_default: mcasp2-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x070, PIN_INPUT, 3)	/* (V24) GPMC0_AD13.MCASP2_ACLKX */
+			J722S_IOPAD(0x06c, PIN_INPUT, 3)	/* (V26) GPMC0_AD12.MCASP2_AFSX */
+			J722S_IOPAD(0x05c, PIN_INPUT, 3)	/* (U27) GPMC0_AD8.MCASP2_AXR0 */
+			J722S_IOPAD(0x060, PIN_OUTPUT, 3)	/* (U26) GPMC0_AD9.MCASP2_AXR1 */
+		>;
+	};
+
+	oldi0_pins_default: oldi0-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x260, PIN_OUTPUT, 0)	/* (AF23) OLDI0_A0N */
+			J722S_IOPAD(0x25c, PIN_OUTPUT, 0)	/* (AG24) OLDI0_A0P */
+			J722S_IOPAD(0x268, PIN_OUTPUT, 0)	/* (AG22) OLDI0_A1N */
+			J722S_IOPAD(0x264, PIN_OUTPUT, 0)	/* (AG23) OLDI0_A1P */
+			J722S_IOPAD(0x270, PIN_OUTPUT, 0)	/* (AB20) OLDI0_A2N */
+			J722S_IOPAD(0x26c, PIN_OUTPUT, 0)	/* (AB21) OLDI0_A2P */
+			J722S_IOPAD(0x278, PIN_OUTPUT, 0)	/* (AG20) OLDI0_A3N */
+			J722S_IOPAD(0x274, PIN_OUTPUT, 0)	/* (AG21) OLDI0_A3P */
+			J722S_IOPAD(0x2a0, PIN_OUTPUT, 0)	/* (AF21) OLDI0_CLK0N */
+			J722S_IOPAD(0x29c, PIN_OUTPUT, 0)	/* (AE20) OLDI0_CLK0P */
+		>;
+	};
+
+	oldi1_pins_default: oldi1-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x280, PIN_OUTPUT, 0)	/* (AD21) OLDI0_A4N */
+			J722S_IOPAD(0x27c, PIN_OUTPUT, 0)	/* (AC21) OLDI0_A4P */
+			J722S_IOPAD(0x288, PIN_OUTPUT, 0)	/* (AF19) OLDI0_A5N */
+			J722S_IOPAD(0x284, PIN_OUTPUT, 0)	/* (AF18) OLDI0_A5P */
+			J722S_IOPAD(0x290, PIN_OUTPUT, 0)	/* (AG17) OLDI0_A6N */
+			J722S_IOPAD(0x28c, PIN_OUTPUT, 0)	/* (AG18) OLDI0_A6P */
+			J722S_IOPAD(0x298, PIN_OUTPUT, 0)	/* (AB19) OLDI0_A7N */
+			J722S_IOPAD(0x294, PIN_OUTPUT, 0)	/* (AA20) OLDI0_A7P */
+			J722S_IOPAD(0x2a8, PIN_OUTPUT, 0)	/* (AD20) OLDI0_CLK1N */
+			J722S_IOPAD(0x2a4, PIN_OUTPUT, 0)	/* (AE19) OLDI0_CLK1P */
+		>;
+	};
+
+	ospi0_pins_default: ospi0-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x000, PIN_OUTPUT, 0)	/* (L24) OSPI0_CLK */
+			J722S_IOPAD(0x02c, PIN_OUTPUT, 0)	/* (K26) OSPI0_CSn0 */
+			J722S_IOPAD(0x030, PIN_OUTPUT, 0)	/* (K23) OSPI0_CSn1 */
+			J722S_IOPAD(0x034, PIN_OUTPUT, 0)	/* (K22) OSPI0_CSn2 */
+			J722S_IOPAD(0x00c, PIN_INPUT, 0)	/* (K27) OSPI0_D0 */
+			J722S_IOPAD(0x010, PIN_INPUT, 0)	/* (L27) OSPI0_D1 */
+			J722S_IOPAD(0x014, PIN_INPUT, 0)	/* (L26) OSPI0_D2 */
+			J722S_IOPAD(0x018, PIN_INPUT, 0)	/* (L25) OSPI0_D3 */
+		>;
+		bootph-all;
+	};
+
+	pcie0_rc_pins_default: pcie0-rc-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x2ac, PIN_OUTPUT, 0)	/* (F25) PCIE0_CLKREQn */
+			J722S_IOPAD(0x1b4, PIN_OUTPUT, 7)	/* (B20) SPI0_CS0.GPIO1_15 */
+		>;
+	};
+
+	pmic_irq_pins_default: pmic-irq-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x090, PIN_INPUT, 7)	/* (P27) GPMC0_BE0n_CLE.GPIO0_35 */
+		>;
+	};
+
+	rgmii1_pins_default: rgmii1-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x14c, PIN_INPUT, 0)	/* (AC25) RGMII1_RD0 */
+			J722S_IOPAD(0x150, PIN_INPUT, 0)	/* (AD27) RGMII1_RD1 */
+			J722S_IOPAD(0x154, PIN_INPUT, 0)	/* (AE24) RGMII1_RD2 */
+			J722S_IOPAD(0x158, PIN_INPUT, 0)	/* (AE26) RGMII1_RD3 */
+			J722S_IOPAD(0x148, PIN_INPUT, 0)	/* (AE27) RGMII1_RXC */
+			J722S_IOPAD(0x144, PIN_INPUT, 0)	/* (AD23) RGMII1_RX_CTL */
+			J722S_IOPAD(0x134, PIN_OUTPUT, 0)	/* (AF27) RGMII1_TD0 */
+			J722S_IOPAD(0x138, PIN_OUTPUT, 0)	/* (AE23) RGMII1_TD1 */
+			J722S_IOPAD(0x13c, PIN_OUTPUT, 0)	/* (AG25) RGMII1_TD2 */
+			J722S_IOPAD(0x140, PIN_OUTPUT, 0)	/* (AF24) RGMII1_TD3 */
+			J722S_IOPAD(0x130, PIN_OUTPUT, 0)	/* (AG26) RGMII1_TXC */
+			J722S_IOPAD(0x12c, PIN_OUTPUT, 0)	/* (AF25) RGMII1_TX_CTL */
+		>;
+	};
+
+	rgmii2_pins_default: rgmii2-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x0f8, PIN_INPUT, 2)	/* (AB24) VOUT0_HSYNC.RGMII2_RD0 */
+			J722S_IOPAD(0x0fc, PIN_INPUT, 2)	/* (AC27) VOUT0_DE.RGMII2_RD1 */
+			J722S_IOPAD(0x100, PIN_INPUT, 2)	/* (AB23) VOUT0_VSYNC.RGMII2_RD2 */
+			J722S_IOPAD(0x104, PIN_INPUT, 2)	/* (AC26) VOUT0_PCLK.RGMII2_RD3 */
+			J722S_IOPAD(0x0f4, PIN_INPUT, 2)	/* (AB27) VOUT0_DATA15.RGMII2_RXC */
+			J722S_IOPAD(0x0f0, PIN_INPUT, 2)	/* (AB26) VOUT0_DATA14.RGMII2_RX_CTL */
+			J722S_IOPAD(0x0e0, PIN_OUTPUT, 2)	/* (AA25) VOUT0_DATA10.RGMII2_TD0 */
+			J722S_IOPAD(0x0e4, PIN_OUTPUT, 2)	/* (AB25) VOUT0_DATA11.RGMII2_TD1 */
+			J722S_IOPAD(0x0e8, PIN_OUTPUT, 2)	/* (AA23) VOUT0_DATA12.RGMII2_TD2 */
+			J722S_IOPAD(0x0ec, PIN_OUTPUT, 2)	/* (AA22) VOUT0_DATA13.RGMII2_TD3 */
+			J722S_IOPAD(0x0dc, PIN_OUTPUT, 2)	/* (AA27) VOUT0_DATA9.RGMII2_TXC */
+			J722S_IOPAD(0x0d8, PIN_OUTPUT, 2)	/* (AA24) VOUT0_DATA8.RGMII2_TX_CTL */
+		>;
+	};
+
+	rtc_pins_default: rtc-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x094, PIN_INPUT, 7)	/* (P26) GPMC0_BE1n.GPIO0_36 */
+		>;
+	};
+
+	sdhci1_pins_default: sdhci1-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x23c, PIN_INPUT, 0)	/* (H22) MMC1_CMD */
+			J722S_IOPAD(0x234, PIN_OUTPUT, 0)	/* (H24) MMC1_CLK */
+			J722S_IOPAD(0x230, PIN_INPUT, 0)	/* (H23) MMC1_DAT0 */
+			J722S_IOPAD(0x22c, PIN_INPUT, 0)	/* (H20) MMC1_DAT1 */
+			J722S_IOPAD(0x228, PIN_INPUT, 0)	/* (J23) MMC1_DAT2 */
+			J722S_IOPAD(0x224, PIN_INPUT, 0)	/* (H25) MMC1_DAT3 */
+			J722S_IOPAD(0x240, PIN_INPUT, 0)	/* (B24) MMC1_SDCD */
+			J722S_IOPAD(0x244, PIN_INPUT, 0)	/* (A24) MMC1_SDWP */
+		>;
+		bootph-all;
+	};
+
+	usb0_connector_pins_default: usb0-connector-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x08c, PIN_INPUT_PULLUP, 7)	/* (N23) GPMC0_WEn.GPIO0_34 */
+		>;
+	};
+
+	usb1_pins_default: usb1-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x258, PIN_OUTPUT, 0)	/* (B27) USB1_DRVVBUS */
+		>;
+	};
+
+	vcc_3p3_sd_s0_pins_default: vcc-3p3-sd-s0-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x01c, PIN_OUTPUT, 7)	/* (L21) OSPI0_D4.GPIO0_7 */
+		>;
+		bootph-all;
+	};
+
+	vcc_3p3_sd_vio_s0_pins_default: vcc-3p3-sd-vio-s0-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x020, PIN_OUTPUT, 7)	/* (M26) OSPI0_D5.GPIO0_8 */
+		>;
+		bootph-all;
+	};
+
+	vcc_3p3_cam_s0_pins_default: vcc-3p3-cam-s0-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x1f0, PIN_OUTPUT, 7)	/* (A23) EXT_REFCLK1.GPIO1_30 */
+		>;
+	};
+
+	vcc_lcd0_panel_pins_default: vcc-lcd0-panel-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x078, PIN_OUTPUT, 7)	/* (V23) GPMC0_AD15.GPIO0_30 */
+		>;
+	};
+
+	vcc_lcd1_panel_pins_default: vcc-lcd1-panel-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x1c4, PIN_OUTPUT, 7)	/* (E20) SPI0_D1.GPIO1_19 */
+		>;
+	};
+
+	vcc_usb0_vbus_pins_default: vcc-usb0-vbus-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x254, PIN_OUTPUT, 7)	/* (E25) USB0_DRVVBUS.GPIO1_50 */
+		>;
+	};
+};
+
+/* SER1 */
+&main_uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart0_pins_default>;
+	bootph-all;
+	status = "okay";
+};
+
+/* SER2 */
+&main_uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart5_pins_default>;
+	bootph-all;
+	status = "okay";
+};
+
+/* I2S0 */
+&mcasp0 {
+	#sound-dai-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcasp0_pins_default>;
+	op-mode = <0>; /* I2S */
+	tdm-slots = <2>;
+	serial-dir = <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>;
+};
+
+/* I2S2 */
+&mcasp2 {
+	#sound-dai-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcasp2_pins_default>;
+	op-mode = <0>; /* I2S */
+	tdm-slots = <2>;
+	serial-dir = <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>;
+};
+
+/* CAN0 */
+&mcu_mcan0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_mcan0_pins_default>;
+	status = "okay";
+};
+
+/* CAN1 */
+&mcu_mcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_mcan1_pins_default>;
+	status = "okay";
+};
+
+&mcu_gpio0 {
+	gpio-line-names =
+		"", "", "", "", "", "", "", "", "", "", "", /* 10 */ "GPIO12",
+		"MCU_INT#", "", "", "", "", "", "", "", "", "", "", "GPIO13";
+};
+
+/* I2C_GP */
+&mcu_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_i2c0_pins_default>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	/* SMARC Module EEPROM */
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+		vcc-supply = <&vcc_1p8_s0>;
+	};
+};
+
+&mcu_pmx0 {
+	mcu_i2c0_pins_default: mcu-i2c0-default-pins {
+		pinctrl-single,pins = <
+			J722S_MCU_IOPAD(0x044, PIN_INPUT, 0)	/* (B13) MCU_I2C0_SCL */
+			J722S_MCU_IOPAD(0x048, PIN_INPUT, 0)	/* (E11) MCU_I2C0_SDA */
+		>;
+	};
+	mcu_mcan0_pins_default: mcu-mcan0-default-pins {
+		pinctrl-single,pins = <
+			J722S_MCU_IOPAD(0x038, PIN_INPUT, 0)	/* (D8) MCU_MCAN0_RX */
+			J722S_MCU_IOPAD(0x034, PIN_OUTPUT, 0)	/* (B2) MCU_MCAN0_TX */
+		>;
+	};
+
+	mcu_mcan1_pins_default: mcu-mcan1-default-pins {
+		pinctrl-single,pins = <
+			J722S_MCU_IOPAD(0x040, PIN_INPUT, 0)	/* (B1) MCU_MCAN1_RX */
+			J722S_MCU_IOPAD(0x03C, PIN_OUTPUT, 0)	/* (C1) MCU_MCAN1_TX */
+		>;
+	};
+
+	mcu_uart0_pins_default: mcu-uart0-default-pins {
+		pinctrl-single,pins = <
+			J722S_MCU_IOPAD(0x014, PIN_INPUT, 0)	/* (B8) MCU_UART0_RXD */
+			J722S_MCU_IOPAD(0x018, PIN_OUTPUT, 0)	/* (B4) MCU_UART0_TXD */
+			J722S_MCU_IOPAD(0x01c, PIN_INPUT, 0)	/* (B5) MCU_UART0_CTSn */
+			J722S_MCU_IOPAD(0x020, PIN_OUTPUT, 0)	/* (C5) MCU_UART0_RTSn */
+		>;
+		bootph-all;
+	};
+
+	mcu_spi0_pins_default: mcu-spi0-default-pins {
+		pinctrl-single,pins = <
+			J722S_MCU_IOPAD(0x008, PIN_OUTPUT, 0)	/* (A9) MCU_SPI0_CLK */
+			J722S_MCU_IOPAD(0x000, PIN_OUTPUT, 0)	/* (C12) MCU_SPI0_CS0 */
+			J722S_MCU_IOPAD(0x004, PIN_OUTPUT, 0)	/* (A10) MCU_SPI0_CS1 */
+			J722S_MCU_IOPAD(0x00c, PIN_INPUT, 0)	/* (B12) MCU_SPI0_D0 */
+			J722S_MCU_IOPAD(0x010, PIN_OUTPUT, 0)	/* (C11) MCU_SPI0_D1 */
+		>;
+	};
+
+	wkup_uart0_pins_default: wkup-uart0-default-pins {
+		pinctrl-single,pins = <
+			J722S_MCU_IOPAD(0x024, PIN_INPUT, 0)	/* (B3) WKUP_UART0_RXD */
+			J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0)	/* (C8) WKUP_UART0_TXD */
+		>;
+		bootph-all;
+	};
+
+	wkup_i2c0_pins_default: wkup-i2c0-default-pins {
+		pinctrl-single,pins = <
+			J722S_MCU_IOPAD(0x04c, PIN_INPUT, 0)	/* (B9) WKUP_I2C0_SCL */
+			J722S_MCU_IOPAD(0x050, PIN_INPUT, 0)	/* (D11) WKUP_I2C0_SDA */
+		>;
+	};
+};
+
+/* SPI0 */
+&mcu_spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_spi0_pins_default>;
+	status = "disabled";
+};
+
+/* SER0 */
+&mcu_uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_uart0_pins_default>;
+	bootph-all;
+	status = "okay";
+};
+
+/* QSPI0 */
+&ospi0 {
+	pinctrl-0 = <&ospi0_pins_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <104000000>;
+		spi-rx-bus-width = <2>;
+		spi-tx-bus-width = <2>;
+		m25p,fast-read;
+		cdns,tshsl-ns = <60>;
+		cdns,tsd2d-ns = <60>;
+		cdns,tchsh-ns = <60>;
+		cdns,tslch-ns = <60>;
+		cdns,read-delay = <3>;
+		vcc-supply = <&vcc_1p8_s0>;
+		bootph-all;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				reg = <0x000000 0x400000>;
+				label = "failsafe bootloader";
+				read-only;
+			};
+		};
+
+		otp-1 {
+			compatible = "user-otp";
+
+			nvmem-layout {
+				compatible = "kontron,sa67-vpd", "kontron,sl28-vpd";
+
+				serial_number: serial-number {
+				};
+
+				base_mac_address: base-mac-address {
+					#nvmem-cell-cells = <1>;
+				};
+			};
+		};
+	};
+};
+
+&pcie0_rc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie0_rc_pins_default>;
+
+	/*
+	 * This is low active, but the driver itself is broken and already
+	 * inverts the logic.
+	 */
+	reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>;
+	phys = <&serdes1_pcie>;
+	phy-names = "pcie-phy";
+	status = "okay";
+};
+
+&sdhci0 {
+	disable-wp;
+	bootph-all;
+	ti,driver-strength-ohm = <50>;
+	status = "okay";
+};
+
+/* SDIO */
+&sdhci1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdhci1_pins_default>;
+	vmmc-supply = <&vcc_3p3_sd_s0>;
+	vqmmc-supply = <&vcc_3p3_sd_vio_s0>;
+	bootph-all;
+	cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>;
+	cd-debounce-delay-ms = <100>;
+	ti,fails-without-test-cd;
+	ti,driver-strength-ohm = <50>;
+	status = "okay";
+};
+
+&serdes_ln_ctrl {
+	idle-states = <J722S_SERDES0_LANE0_USB>,
+		      <J722S_SERDES1_LANE0_PCIE0_LANE0>;
+};
+
+&serdes_wiz0 {
+	status = "okay";
+};
+
+&serdes_wiz1 {
+	status = "okay";
+};
+
+&serdes0 {
+	serdes0_usb3: phy@0 {
+		reg = <0>;
+		#phy-cells = <0>;
+		resets = <&serdes_wiz0 1>;
+		cdns,num-lanes = <1>;
+		cdns,phy-type = <PHY_TYPE_USB3>;
+	};
+};
+
+&serdes1 {
+	serdes1_pcie: phy@0 {
+		reg = <0>;
+		#phy-cells = <0>;
+		resets = <&serdes_wiz1 1>;
+		cdns,num-lanes = <1>;
+		cdns,phy-type = <PHY_TYPE_PCIE>;
+	};
+};
+
+&usb0 {
+	/* dual role is implemented but not a full featured OTG */
+	adp-disable;
+	hnp-disable;
+	srp-disable;
+	dr_mode = "otg";
+	usb-role-switch;
+	role-switch-default-mode = "peripheral";
+	status = "okay";
+
+	port {
+		usb0_hc: endpoint {
+			remote-endpoint = <&usb0_connector>;
+		};
+	};
+};
+
+&usb1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb1_pins_default>;
+
+	dr_mode = "host";
+	maximum-speed = "super-speed";
+	phys = <&serdes0_usb3>;
+	phy-names = "cdns3,usb3-phy";
+};
+
+&usbss0 {
+	ti,vbus-divider;
+	status = "okay";
+};
+
+&usbss1 {
+	ti,vbus-divider;
+	status = "okay";
+};
+
+/* I2C_PM */
+&wkup_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&wkup_i2c0_pins_default>;
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+/* SER3 */
+&wkup_uart0 {
+	/* WKUP UART0 is used by Device Manager firmware */
+	pinctrl-names = "default";
+	pinctrl-0 = <&wkup_uart0_pins_default>;
+	bootph-all;
+	status = "reserved";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso
new file mode 100644
index 000000000000..4e9eb7998f38
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso
@@ -0,0 +1,19 @@
+/dts-v1/;
+/plugin/;
+
+&cpsw3g_mdio {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
+&cpsw_port2 {
+	phy-connection-type = "rgmii-id";
+	phy-handle = <&phy1>;
+	nvmem-cells = <&base_mac_address 1>;
+	nvmem-cell-names = "mac-address";
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso
new file mode 100644
index 000000000000..c9aa15269c92
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso
@@ -0,0 +1,24 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&{/} {
+	aliases {
+		rtc0 = "/bus@f0000/i2c@20000000/rtc@51"; /* &rtc */
+		rtc1 = "/bus@f0000/bus@b00000/rtc@2b1f0000"; /* &wkup_rtc0 */
+	};
+};
+
+&main_i2c0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	rtc: rtc@51 {
+		compatible = "microcrystal,rv8263";
+		reg = <0x51>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtc_pins_default>;
+		interrupts-extended = <&main_gpio0 36 IRQ_TYPE_EDGE_FALLING>;
+	};
+};
-- 
2.39.5

Re: [PATCH v1 0/7] Initial Kontron SMARC-sAM67 support

[Nishanth Menon]

On 15:15-20250822, Michael Walle wrote:
> Now that the PMIC support is there, we can finally, upstream the
> support for this board. Besides the usual device tree, this
> patchset contains the support for the on-board house keeping MCU. It
> make extensive reuse of the drivers for the former SMARC-sAL28
> board. Besides different hwmon sensors, all the dt binding patches
> will just add a board specific compatible (in addition to the old
> sl28 compatible) to make any future board specific quirks possible.
> 
> I'm aware that there is a patch [1] which moves the sl28cpld MFD
> schema to a different directory. Once that patch is merged, I'll
> repost this series. But I already want to get some early feedback.
> 
> [1] https://lore.kernel.org/r/20250822075712.27314-2-krzysztof.kozlowski@linaro.org/
> 
> Michael Walle (7):
>   dt-bindings: arm: ti: Add bindings for Kontron SMARC-sAM67 module
>   dt-bindings: mfd: sl28cpld: add sa67mcu compatible
>   dt-bindings: hwmon: sl28cpld: add sa67mcu compatible
>   dt-bindings: watchdog: add SMARC-sAM67 support
>   dt-bindings: nvmem: sl28cpld: add sa67mcu compatible
>   hwmon: sl28cpld: add SMARC-sAM67 support
>   arm64: dts: ti: Add support for Kontron SMARC-sAM67

Since this goes through multiple maintainers, may I suggest the
following strategy?

for this window:
* send dts and board binding changes dropping the nodes that are yet to
 be upstream
* send the compatible changes to each of the maintainers

Next window:
* add the nodes based on acceptance of the driver bindings

This removes multiple maintainers needing to give me immutable tags etc.

What do you think?
> 
>  .../devicetree/bindings/arm/ti/k3.yaml        |    1 +
>  .../hwmon/kontron,sl28cpld-hwmon.yaml         |    1 +
>  .../bindings/mfd/kontron,sl28cpld.yaml        |    7 +-
>  .../nvmem/layouts/kontron,sl28-vpd.yaml       |    7 +-
>  .../watchdog/kontron,sl28cpld-wdt.yaml        |    7 +-
>  arch/arm64/boot/dts/ti/Makefile               |    6 +
>  .../dts/ti/k3-am67a-kontron-sa67-base.dts     | 1092 +++++++++++++++++
>  .../dts/ti/k3-am67a-kontron-sa67-gbe1.dtso    |   19 +
>  .../ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso  |   24 +
>  drivers/hwmon/sl28cpld-hwmon.c                |   76 +-
>  10 files changed, 1234 insertions(+), 6 deletions(-)
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso
> 
> -- 
> 2.39.5
> 

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D
https://ti.com/opensource

Re: [PATCH v1 0/7] Initial Kontron SMARC-sAM67 support

[Rob Herring (Arm)]

On Fri, 22 Aug 2025 15:15:24 +0200, Michael Walle wrote:
> Now that the PMIC support is there, we can finally, upstream the
> support for this board. Besides the usual device tree, this
> patchset contains the support for the on-board house keeping MCU. It
> make extensive reuse of the drivers for the former SMARC-sAL28
> board. Besides different hwmon sensors, all the dt binding patches
> will just add a board specific compatible (in addition to the old
> sl28 compatible) to make any future board specific quirks possible.
> 
> I'm aware that there is a patch [1] which moves the sl28cpld MFD
> schema to a different directory. Once that patch is merged, I'll
> repost this series. But I already want to get some early feedback.
> 
> [1] https://lore.kernel.org/r/20250822075712.27314-2-krzysztof.kozlowski@linaro.org/
> 
> Michael Walle (7):
>   dt-bindings: arm: ti: Add bindings for Kontron SMARC-sAM67 module
>   dt-bindings: mfd: sl28cpld: add sa67mcu compatible
>   dt-bindings: hwmon: sl28cpld: add sa67mcu compatible
>   dt-bindings: watchdog: add SMARC-sAM67 support
>   dt-bindings: nvmem: sl28cpld: add sa67mcu compatible
>   hwmon: sl28cpld: add SMARC-sAM67 support
>   arm64: dts: ti: Add support for Kontron SMARC-sAM67
> 
>  .../devicetree/bindings/arm/ti/k3.yaml        |    1 +
>  .../hwmon/kontron,sl28cpld-hwmon.yaml         |    1 +
>  .../bindings/mfd/kontron,sl28cpld.yaml        |    7 +-
>  .../nvmem/layouts/kontron,sl28-vpd.yaml       |    7 +-
>  .../watchdog/kontron,sl28cpld-wdt.yaml        |    7 +-
>  arch/arm64/boot/dts/ti/Makefile               |    6 +
>  .../dts/ti/k3-am67a-kontron-sa67-base.dts     | 1092 +++++++++++++++++
>  .../dts/ti/k3-am67a-kontron-sa67-gbe1.dtso    |   19 +
>  .../ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso  |   24 +
>  drivers/hwmon/sl28cpld-hwmon.c                |   76 +-
>  10 files changed, 1234 insertions(+), 6 deletions(-)
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso
> 
> --
> 2.39.5
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: attempting to guess base-commit...
 Base: tags/next-20250822 (exact match)

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/ti/' for 20250822131531.1366437-1-mwalle@kernel.org:

arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dtb: pmic@44 (ti,tps652g1): 'gpio-line-names' does not match any of the regexes: '^buck([1-5]|12|34|123|1234)-supply$', '^ldo[1-4]-supply$', '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/mfd/ti,tps6594.yaml#

Re: [PATCH v1 0/7] Initial Kontron SMARC-sAM67 support

[Michael Walle]

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On Fri Aug 22, 2025 at 5:23 PM CEST, Nishanth Menon wrote:
> On 15:15-20250822, Michael Walle wrote:
> > Now that the PMIC support is there, we can finally, upstream the
> > support for this board. Besides the usual device tree, this
> > patchset contains the support for the on-board house keeping MCU. It
> > make extensive reuse of the drivers for the former SMARC-sAL28
> > board. Besides different hwmon sensors, all the dt binding patches
> > will just add a board specific compatible (in addition to the old
> > sl28 compatible) to make any future board specific quirks possible.
> > 
> > I'm aware that there is a patch [1] which moves the sl28cpld MFD
> > schema to a different directory. Once that patch is merged, I'll
> > repost this series. But I already want to get some early feedback.
> > 
> > [1] https://lore.kernel.org/r/20250822075712.27314-2-krzysztof.kozlowski@linaro.org/
> > 
> > Michael Walle (7):
> >   dt-bindings: arm: ti: Add bindings for Kontron SMARC-sAM67 module
> >   dt-bindings: mfd: sl28cpld: add sa67mcu compatible
> >   dt-bindings: hwmon: sl28cpld: add sa67mcu compatible
> >   dt-bindings: watchdog: add SMARC-sAM67 support
> >   dt-bindings: nvmem: sl28cpld: add sa67mcu compatible
> >   hwmon: sl28cpld: add SMARC-sAM67 support
> >   arm64: dts: ti: Add support for Kontron SMARC-sAM67
>
> Since this goes through multiple maintainers, may I suggest the
> following strategy?
>
> for this window:
> * send dts and board binding changes dropping the nodes that are yet to
>  be upstream
> * send the compatible changes to each of the maintainers
>
> Next window:
> * add the nodes based on acceptance of the driver bindings
>
> This removes multiple maintainers needing to give me immutable tags etc.
>
> What do you think?

Not sure, if this needs an IB anyway or if the DTS can be pulled by
the corresponding SoC subsys and the DT binding can go through
another tree in the same cycle. If not, I can certainly split the
device tree (to my knowledge, it was said that it should be a
complete description :).

I'd expect that Lee is picking up the first 6 patches after they got
an ACK. Please correct me if I'm wrong, Lee.

In any case, I'd give this v1 some time to get some feedback on the
patches.

-michael

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Re: [PATCH v1 1/7] dt-bindings: arm: ti: Add bindings for Kontron SMARC-sAM67 module

[Krzysztof Kozlowski]

On 22/08/2025 15:15, Michael Walle wrote:
> Add devicetree bindings for the AM67 based Kontron SMARC-sAM67
> module.
> 
You can drop "bindings for" in the subject.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v1 0/7] Initial Kontron SMARC-sAM67 support

[Michael Walle]

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On Fri Aug 22, 2025 at 11:27 PM CEST, Rob Herring (Arm) wrote:
> New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/ti/' for 20250822131531.1366437-1-mwalle@kernel.org:
>
> arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dtb: pmic@44 (ti,tps652g1): 'gpio-line-names' does not match any of the regexes: '^buck([1-5]|12|34|123|1234)-supply$', '^ldo[1-4]-supply$', '^pinctrl-[0-9]+$'
> 	from schema $id: http://devicetree.org/schemas/mfd/ti,tps6594.yaml#

Damn, very late change on the device tree :o I'll add a new patch to add

  gpio-line-names: true

to bindings/mfd/ti,tps6594.yaml

-michael

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Re: [PATCH v1 0/7] Initial Kontron SMARC-sAM67 support

[Michael Walle]

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> I'd expect that Lee is picking up the first 6 patches after they got
> an ACK. Please correct me if I'm wrong, Lee.

Ah my bad, patches 2-6, i.e. everything belonging to the MFD driver.

-michael

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Re: [PATCH v1 2/7] dt-bindings: mfd: sl28cpld: add sa67mcu compatible

[Krzysztof Kozlowski]

On 22/08/2025 15:15, Michael Walle wrote:
> The Kontron SMARC-sAM67 module features an on-board house keeping uC.
> It's designed to be compatible with the older on-board CPLD used on the
> SMARC-sAL28 board. To be prepared for any board specific quirks, add a
> specific compatible.
> 
> Signed-off-by: Michael Walle <mwalle@kernel.org>
> ---



A note: this will conflict with my patches moving it to embedded-controller.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v1 3/7] dt-bindings: hwmon: sl28cpld: add sa67mcu compatible

[Krzysztof Kozlowski]

On 22/08/2025 15:15, Michael Walle wrote:
> The Kontron SMARC-sAM67 module features an on-board house keeping uC.
> It is designed to be compatible with the older sl28cpld implementation,
> but has different sensors, like voltage and temperature monitoring. Add
> a new compatible for that board.
> 
> Signed-off-by: Michael Walle <mwalle@kernel.org>
> ---
>  .../devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml        | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml b/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml
> index 010333cb25c0..0275803e843c 100644
> --- a/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml
> +++ b/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml
> @@ -17,6 +17,7 @@ properties:
>    compatible:
>      enum:
>        - kontron,sl28cpld-fan
> +      - kontron,sa67mcu-hwmon

Please keep sorting alphabetically.

With this fixed:

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v1 5/7] dt-bindings: nvmem: sl28cpld: add sa67mcu compatible

[Krzysztof Kozlowski]

On 22/08/2025 15:15, Michael Walle wrote:
> The Kontron SMARC-sAM67 has the same nvmem layout as the SMARC-sAL28. To
> To be prepared for any board specific quirks, add a specific compatible.
> 
> Signed-off-by: Michael Walle <mwalle@kernel.org>
> ---
>  .../bindings/nvmem/layouts/kontron,sl28-vpd.yaml           | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 



Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v1 4/7] dt-bindings: watchdog: add SMARC-sAM67 support

[Krzysztof Kozlowski]

On 22/08/2025 15:15, Michael Walle wrote:
> The SMARC-sAM67 board has an on-board uC which has the same register
> interface as the older CPLD implementation on the SMARC-sAL28 board.
> Although the MCU emulates the same behavior, be prepared for any quirks
> and add a board specific compatible.
> 
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v1 7/7] arm64: dts: ti: Add support for Kontron SMARC-sAM67

[Andrew Davis]

On 8/22/25 8:15 AM, Michael Walle wrote:
> The Kontron SMARC-sAM67 is a SMARC module which features a TI AM67 SoC.
> It supports the following features:
>   * Quad-core AM67A94 with 1.4GHz
>   * 8 GiB RAM
>   * 64 GiB eMMC
>   * 4 MiB SPI flash for failsafe booting
>   * 4x UART
>   * 1x USB 2.0
>   * 1x USB 3.2 (or 4x USB3.2 with onboard USB 3.2 hub)
>   * 1x RTC
>   * 2x GBE
>   * 1x QSPI (with 2 chip selects)
>   * 1x SPI (with 2 chip selects)
>   * 7x I2C
>   * 4x CSI (*)
>   * 2x LVDS (or one dual-link LVDS)
>   * 1x DSI (*)
>   * 1x DP (*)
>   * onboard microcontroller for boot control, failsafe booting and
>     external watchdog
> 
> (*) not yet supported by the kernel
> 
> There is a base device tree and overlays which will add optional
> features. At the moment there is one full featured variant of that
> board whose device tree is generated during build by merging all the
> device tree overlays.
> 
> Signed-off-by: Michael Walle <mwalle@kernel.org>
> ---
>   arch/arm64/boot/dts/ti/Makefile               |    6 +
>   .../dts/ti/k3-am67a-kontron-sa67-base.dts     | 1092 +++++++++++++++++
>   .../dts/ti/k3-am67a-kontron-sa67-gbe1.dtso    |   19 +
>   .../ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso  |   24 +
>   4 files changed, 1141 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts
>   create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso
>   create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso
> 
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile

[...]

> diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso
> new file mode 100644
> index 000000000000..4e9eb7998f38
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso
> @@ -0,0 +1,19 @@

DTSO files should have copyright and license here same as DTS.

Andrew

> +/dts-v1/;
> +/plugin/;
> +
> +&cpsw3g_mdio {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	phy1: ethernet-phy@1 {
> +		reg = <1>;
> +	};
> +};
> +
> +&cpsw_port2 {
> +	phy-connection-type = "rgmii-id";
> +	phy-handle = <&phy1>;
> +	nvmem-cells = <&base_mac_address 1>;
> +	nvmem-cell-names = "mac-address";
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso
> new file mode 100644
> index 000000000000..c9aa15269c92
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso
> @@ -0,0 +1,24 @@
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +&{/} {
> +	aliases {
> +		rtc0 = "/bus@f0000/i2c@20000000/rtc@51"; /* &rtc */
> +		rtc1 = "/bus@f0000/bus@b00000/rtc@2b1f0000"; /* &wkup_rtc0 */
> +	};
> +};
> +
> +&main_i2c0 {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	rtc: rtc@51 {
> +		compatible = "microcrystal,rv8263";
> +		reg = <0x51>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&rtc_pins_default>;
> +		interrupts-extended = <&main_gpio0 36 IRQ_TYPE_EDGE_FALLING>;
> +	};
> +};