From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59AACCA0EED for ; Mon, 25 Aug 2025 03:16:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=CCe5L0csbysWCAQAXGClB5ZlpD9pY8zUZkyz6n8jnUY=; b=C8Oj+LEQ3C/+vFvgWPMV65rtrj RZnjPd1BOA0WPLuqw/UW72hPtp/JShZPI31Rya6NzC2q9x7lUETFoNeQW5gaOUkczoMtMLswLgWps E5K/MeMrsSwm1TDIcTOaM/f5NC1fkjdbMPWr1WDj1B5KnnSSRPOvKBT4GtrodXEMy/A1yGeX1qRPM DCepwuf533AUFqKOfFQrxJeUp++tUhvLdVWW9wy7I4igDLRUmqYT1DwBFQsP2YG/7/hpWrRnfrtHV BUnWwJhmejq54XZTgH+KSrpHa799mgO7D0DV23zAfFJF1QmcOMFzKiQFCYJF2eTW6hwptCfWhYsdJ PXOY20VA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uqNhV-00000006nUP-1UDG; Mon, 25 Aug 2025 03:16:53 +0000 Received: from mail-qt1-x833.google.com ([2607:f8b0:4864:20::833]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uqNN7-00000006lWV-04Cm for linux-arm-kernel@lists.infradead.org; Mon, 25 Aug 2025 02:55:51 +0000 Received: by mail-qt1-x833.google.com with SMTP id d75a77b69052e-4b1258a3d71so46162081cf.2 for ; Sun, 24 Aug 2025 19:55:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1756090548; x=1756695348; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=CCe5L0csbysWCAQAXGClB5ZlpD9pY8zUZkyz6n8jnUY=; b=LMQ3y3ruT9Ux3A8xpx6aKN1FbtFQvlIOr8Ky2BVaFX6dK4aoI0ZFs8jEBSkVbjYnQ2 HEujOoXGGaw2v8GCaEBOI4nJOX26IyzRM2ZhBYrsHb8WLCivXzF4VDDZgOFG4v8UCWet 6fOjriYW5vJ3ushCWn1XpPOdGintw4ieLpNvmcaKxsiNJDs/OzF1PD9kq1BCpCtLSEG1 LjfFcFAa5BVmAUXz6zdjb8XO08A65JF7J+aPBM40Cmxw84Mr50dtXrSjssMNRYszoT7z rrvTQSQpiUNQg5vwWOb+KCzAIt8WZIzzVlW+I0H2GZJDJqNgdcqs3kLp1oqBYSxCGOSb 4IMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756090548; x=1756695348; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CCe5L0csbysWCAQAXGClB5ZlpD9pY8zUZkyz6n8jnUY=; b=QJEzp+EDnTbxAiu7FZBU3fxcjqNmacG304JlzBUSmkCU3k59v1t4o/jYARfNNkwoPm ufzwRW0abeZjWA3POpU33wmy861XpIdodSwmhRpGFRpVsO6gJ0QBqzLq2hK9TaW9XT0H pl4Cv44/x1UhJ/K/qmZPH+OgWcg0lnCCR6r6XfVYU1hED2DnE/qbI7bDjUK1V1Bkuw6w 4hFo2vBSp6kHf4dGincIAlHAAxUpL7jjKWwoRhJMr/nV4nh5RDuOAa9XSjWfJCNN+4HD MwguIyjlqrl38wKhMlYy/aZrwX5Mk4M2uTpRhbbgpS3wLjrV0j0RerbLY5iw4jxON6K5 WXMg== X-Forwarded-Encrypted: i=1; AJvYcCXzFOXXDFBKFU7v4Kqh1zVmdt9xfiFvBZH6nlLMxY1MwanYxtg6UCGFZOFi0NyWHWqoNAtmJ2byS3QYQDj7G1J6@lists.infradead.org X-Gm-Message-State: AOJu0Yyy1RMLRLfllfVAOSRd7ryFfp+U75JUyaq9QATY0ZUU6u92JN6V NsBA1Qo9IHdvp400z4RJ9qJ9u1TkTccumpPo+Q35UB9WR13Z0VjbPSow X-Gm-Gg: ASbGncs8yT+tIDWwtAbjqhX9FEa+BxKBk/CDAGlMGTjda3CCHuCZQ9H8hIVL4DZQaMW 4dW/M0ZDm4QG1/Y6t173BWlAJf01ozFxCv/nQnG4gNuPFFaUK6wdHKDGB0UR4bmKRvyWyq2V6z5 yfnFcTgzmowEpIOBdWr7X/251w1NrmCmX09KAU1AVeCiIushPk+66ID87KFv1tpuAvrC1q0vtEs TFRUm3+57Xd/9onylniQjNWscf2eMVL2KIu7t7FMNf4rV3ItIMrPPoy3ZyQYiwXROoEIfmvobAZ tZc2mzlLGWZeFXOIZoknEFmBoFD3EvXS1o2yYgz3CjhIYiIDF4Y5ZL5AYUDH8vML1BfUVDMISfP 5Hq+OW8YfFBKDnDFQKe1GmJp9K+tHkw== X-Google-Smtp-Source: AGHT+IHgUZ9+Jx3/fy4Dl0nJjG319S4p/fQ+Si7LSCfcEkeSLWjn+z71kEZ/k9GyFMLhulYyDv0T7g== X-Received: by 2002:ac8:5992:0:b0:4b2:8ac5:27c5 with SMTP id d75a77b69052e-4b2aab52f84mr111438831cf.80.1756090547883; Sun, 24 Aug 2025 19:55:47 -0700 (PDT) Received: from [127.0.0.1] ([172.191.151.57]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4b2b8c61adcsm43970491cf.5.2025.08.24.19.55.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Aug 2025 19:55:47 -0700 (PDT) From: Denzeel Oliva Date: Mon, 25 Aug 2025 02:55:46 +0000 Subject: [PATCH v3 4/4] clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250825-cmu-top-v3-4-8838641432dc@gmail.com> References: <20250825-cmu-top-v3-0-8838641432dc@gmail.com> In-Reply-To: <20250825-cmu-top-v3-0-8838641432dc@gmail.com> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Denzeel Oliva X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1756090544; l=10122; i=wachiturroxd150@gmail.com; s=20250825; h=from:subject:message-id; bh=WFncasnVl4c9X1Gr26kTZOOG/41f6AQgcFmAGnTMK1Q=; b=FT6mepiwgP1FOw/ojGNuM3AGv/aJwejE//K73Nl21KtOkxB0DscG/Zb6AFVy0H53O9WVtvQmI Z2YTGD2k2BkCWiBl4qgdCAmnYnpSlVdcbw08DY+auR7LaBSAJpbjFOX X-Developer-Key: i=wachiturroxd150@gmail.com; a=ed25519; pk=qZrip2idhSTNQABELWG6WKCrg9xOKep//pV9JGKmW5k= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250824_195549_063669_0C21BE18 X-CRM114-Status: GOOD ( 12.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Switch PLL muxes to PLL_CON0 to correct parent selection and clock rates. Add DPU_BUS and CMUREF mux/div and their register hooks and parents. Signed-off-by: Denzeel Oliva --- drivers/clk/samsung/clk-exynos990.c | 97 ++++++++++++++++++++++++------------- 1 file changed, 63 insertions(+), 34 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c index 59b05ea55..d4d932c48 100644 --- a/drivers/clk/samsung/clk-exynos990.c +++ b/drivers/clk/samsung/clk-exynos990.c @@ -45,6 +45,7 @@ #define PLL_CON3_PLL_SHARED3 0x024c #define PLL_CON0_PLL_SHARED4 0x0280 #define PLL_CON3_PLL_SHARED4 0x028c +#define CLK_CON_MUX_CLKCMU_DPU_BUS 0x1000 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008 #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x100c @@ -103,6 +104,8 @@ #define CLK_CON_MUX_MUX_CLKCMU_SSP_BUS 0x10e0 #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10e4 #define CLK_CON_MUX_MUX_CLKCMU_VRA_BUS 0x10e8 +#define CLK_CON_MUX_MUX_CLK_CMU_CMUREF 0x10f0 +#define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1800 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1804 #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1808 @@ -162,6 +165,7 @@ #define CLK_CON_DIV_CLKCMU_VRA_BUS 0x18e0 #define CLK_CON_DIV_DIV_CLKCMU_DPU 0x18e8 #define CLK_CON_DIV_DIV_CLKCMU_DPU_ALT 0x18ec +#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18f0 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18f4 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18f8 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18fc @@ -239,13 +243,21 @@ static const unsigned long top_clk_regs[] __initconst = { PLL_LOCKTIME_PLL_SHARED2, PLL_LOCKTIME_PLL_SHARED3, PLL_LOCKTIME_PLL_SHARED4, + PLL_CON0_PLL_G3D, PLL_CON3_PLL_G3D, + PLL_CON0_PLL_MMC, PLL_CON3_PLL_MMC, + PLL_CON0_PLL_SHARED0, PLL_CON3_PLL_SHARED0, + PLL_CON0_PLL_SHARED1, PLL_CON3_PLL_SHARED1, + PLL_CON0_PLL_SHARED2, PLL_CON3_PLL_SHARED2, + PLL_CON0_PLL_SHARED3, PLL_CON3_PLL_SHARED3, + PLL_CON0_PLL_SHARED4, PLL_CON3_PLL_SHARED4, + CLK_CON_MUX_CLKCMU_DPU_BUS, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, @@ -304,6 +316,8 @@ static const unsigned long top_clk_regs[] __initconst = { CLK_CON_MUX_MUX_CLKCMU_SSP_BUS, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, + CLK_CON_MUX_MUX_CLK_CMU_CMUREF, + CLK_CON_MUX_MUX_CMU_CMUREF, CLK_CON_DIV_CLKCMU_APM_BUS, CLK_CON_DIV_CLKCMU_AUD_CPU, CLK_CON_DIV_CLKCMU_BUS0_BUS, @@ -363,6 +377,7 @@ static const unsigned long top_clk_regs[] __initconst = { CLK_CON_DIV_CLKCMU_VRA_BUS, CLK_CON_DIV_DIV_CLKCMU_DPU, CLK_CON_DIV_DIV_CLKCMU_DPU_ALT, + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, CLK_CON_DIV_PLL_SHARED0_DIV2, CLK_CON_DIV_PLL_SHARED0_DIV3, CLK_CON_DIV_PLL_SHARED0_DIV4, @@ -458,6 +473,8 @@ PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" }; PNAME(mout_pll_shared4_p) = { "oscclk", "fout_shared4_pll" }; PNAME(mout_pll_mmc_p) = { "oscclk", "fout_mmc_pll" }; PNAME(mout_pll_g3d_p) = { "oscclk", "fout_g3d_pll" }; +PNAME(mout_cmu_dpu_bus_p) = { "dout_cmu_dpu", + "dout_cmu_dpu_alt" }; PNAME(mout_cmu_apm_bus_p) = { "dout_cmu_shared0_div2", "dout_cmu_shared2_div2" }; PNAME(mout_cmu_aud_cpu_p) = { "dout_cmu_shared0_div2", @@ -507,7 +524,7 @@ PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared4_pll", "dout_cmu_shared0_div2", "fout_shared2_pll", "dout_cmu_shared0_div4" }; -PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared4_pll", +PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared4_pll", "dout_cmu_shared0_div2", "fout_shared2_pll", "dout_cmu_shared0_div4" }; @@ -577,7 +594,7 @@ PNAME(mout_cmu_hsi1_bus_p) = { "dout_cmu_shared0_div3", "dout_cmu_shared4_div3", "dout_cmu_shared2_div2", "fout_mmc_pll", "oscclk", "oscclk" }; -PNAME(mout_cmu_hsi1_mmc_card_p) = { "oscclk", "fout_shared2_pll", +PNAME(mout_cmu_hsi1_mmc_card_p) = { "oscclk", "fout_shared2_pll", "fout_mmc_pll", "dout_cmu_shared0_div4" }; PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "fout_shared2_pll" }; @@ -672,6 +689,12 @@ PNAME(mout_cmu_vra_bus_p) = { "dout_cmu_shared0_div3", "dout_cmu_shared4_div2", "dout_cmu_shared0_div4", "dout_cmu_shared4_div3" }; +PNAME(mout_cmu_cmuref_p) = { "oscclk", + "dout_cmu_clk_cmuref" }; +PNAME(mout_cmu_clk_cmuref_p) = { "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "oscclk" }; /* * Register name to clock name mangling strategy used in this file @@ -689,19 +712,21 @@ PNAME(mout_cmu_vra_bus_p) = { "dout_cmu_shared0_div3", static const struct samsung_mux_clock top_mux_clks[] __initconst = { MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p, - PLL_CON3_PLL_SHARED0, 4, 1), + PLL_CON0_PLL_SHARED0, 4, 1), MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p, - PLL_CON3_PLL_SHARED1, 4, 1), + PLL_CON0_PLL_SHARED1, 4, 1), MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p, - PLL_CON3_PLL_SHARED2, 4, 1), + PLL_CON0_PLL_SHARED2, 4, 1), MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p, - PLL_CON3_PLL_SHARED3, 4, 1), + PLL_CON0_PLL_SHARED3, 4, 1), MUX(CLK_MOUT_PLL_SHARED4, "mout_pll_shared4", mout_pll_shared4_p, PLL_CON0_PLL_SHARED4, 4, 1), MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p, PLL_CON0_PLL_MMC, 4, 1), MUX(CLK_MOUT_PLL_G3D, "mout_pll_g3d", mout_pll_g3d_p, PLL_CON0_PLL_G3D, 4, 1), + MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus", + mout_cmu_dpu_bus_p, CLK_CON_MUX_CLKCMU_DPU_BUS, 0, 1), MUX(CLK_MOUT_CMU_APM_BUS, "mout_cmu_apm_bus", mout_cmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1), MUX(CLK_MOUT_CMU_AUD_CPU, "mout_cmu_aud_cpu", @@ -830,37 +855,13 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = { mout_cmu_tnr_bus_p, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3), MUX(CLK_MOUT_CMU_VRA_BUS, "mout_cmu_vra_bus", mout_cmu_vra_bus_p, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, 0, 2), + MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", + mout_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), + MUX(CLK_MOUT_CMU_CLK_CMUREF, "mout_cmu_clk_cmuref", + mout_cmu_clk_cmuref_p, CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0, 2), }; static const struct samsung_div_clock top_div_clks[] __initconst = { - /* SHARED0 region*/ - DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0", - CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), - DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0", - CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), - DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0_div2", - CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), - - /* SHARED1 region*/ - DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", "mout_pll_shared1", - CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), - DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", "mout_pll_shared1", - CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), - DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", "dout_cmu_shared1_div2", - CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), - - /* SHARED2 region */ - DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", "mout_pll_shared2", - CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1), - - /* SHARED4 region*/ - DIV(CLK_DOUT_CMU_SHARED4_DIV2, "dout_cmu_shared4_div2", "mout_pll_shared4", - CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1), - DIV(CLK_DOUT_CMU_SHARED4_DIV3, "dout_cmu_shared4_div3", "mout_pll_shared4", - CLK_CON_DIV_PLL_SHARED4_DIV3, 0, 2), - DIV(CLK_DOUT_CMU_SHARED4_DIV4, "dout_cmu_shared4_div4", "mout_pll_shared4", - CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1), - DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 2), DIV(CLK_DOUT_CMU_AUD_CPU, "dout_cmu_aud_cpu", "gout_cmu_aud_cpu", @@ -974,6 +975,34 @@ static const struct samsung_div_clock top_div_clks[] __initconst = { CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4), DIV(CLK_DOUT_CMU_DPU, "dout_cmu_dpu", "gout_cmu_dpu", CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3), + DIV(CLK_DOUT_CMU_DPU_ALT, "dout_cmu_dpu_alt", "gout_cmu_dpu_bus", + CLK_CON_DIV_DIV_CLKCMU_DPU_ALT, 0, 4), + DIV(CLK_DOUT_CMU_CLK_CMUREF, "dout_cmu_clk_cmuref", "mout_cmu_clk_cmuref", + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2), + /* SHARED0 region*/ + DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0", + CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), + DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0", + CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), + DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0_div2", + CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), + /* SHARED1 region*/ + DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", "mout_pll_shared1", + CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), + DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", "mout_pll_shared1", + CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), + DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", "dout_cmu_shared1_div2", + CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), + /* SHARED2 region */ + DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", "mout_pll_shared2", + CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1), + /* SHARED4 region*/ + DIV(CLK_DOUT_CMU_SHARED4_DIV2, "dout_cmu_shared4_div2", "mout_pll_shared4", + CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1), + DIV(CLK_DOUT_CMU_SHARED4_DIV3, "dout_cmu_shared4_div3", "mout_pll_shared4", + CLK_CON_DIV_PLL_SHARED4_DIV3, 0, 2), + DIV(CLK_DOUT_CMU_SHARED4_DIV4, "dout_cmu_shared4_div4", "dout_cmu_shared4_div2", + CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1), }; static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = { -- 2.50.1