From: Anand Moon <linux.amoon@gmail.com>
To: Neil Armstrong <neil.armstrong@linaro.org>,
Kevin Hilman <khilman@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic
Meson SoC support),
linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson
SoC support),
devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND
FLATTENED DEVICE TREE BINDINGS),
linux-kernel@vger.kernel.org (open list)
Cc: Anand Moon <linux.amoon@gmail.com>
Subject: [PATCH v2 11/11] arm64: dts: amlogic: Add cache information to the Amlogic T7 SoC
Date: Mon, 25 Aug 2025 12:21:51 +0530 [thread overview]
Message-ID: <20250825065240.22577-12-linux.amoon@gmail.com> (raw)
In-Reply-To: <20250825065240.22577-1-linux.amoon@gmail.com>
As per T7 datasheet add missing cache information to the Amlogic T7 SoC.
- Each Cortex-A53 core has 32 KB of instruction cache and
32 KB of L1 data cache available.
- Each Cortex-A73 core has 64 KB of L1 instruction cache and
64 KB of L1 data cache available.
- The little (A53) cluster has 256 KB of unified L2 cache available.
- The big (A73) cluster has 1 MB of unified L2 cache available.
Cache memory significantly reduces the time it takes for the CPU
to access data and instructions, leading to faster program execution
and overall system responsiveness.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 74 +++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
index ec743cad57db..6510068bcff9 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
@@ -53,6 +53,13 @@ cpu100: cpu@100 {
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2_cache_l>;
};
cpu101: cpu@101 {
@@ -60,6 +67,13 @@ cpu101: cpu@101 {
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2_cache_l>;
};
cpu102: cpu@102 {
@@ -67,6 +81,13 @@ cpu102: cpu@102 {
compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2_cache_l>;
};
cpu103: cpu@103 {
@@ -74,6 +95,13 @@ cpu103: cpu@103 {
compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2_cache_l>;
};
cpu0: cpu@0 {
@@ -81,6 +109,13 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a73";
reg = <0x0 0x0>;
enable-method = "psci";
+ d-cache-line-size = <64>;
+ d-cache-size = <0x10000>;
+ d-cache-sets = <64>;
+ i-cache-line-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <64>;
+ next-level-cache = <&l2_cache_b>;
};
cpu1: cpu@1 {
@@ -88,6 +123,13 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a73";
reg = <0x0 0x1>;
enable-method = "psci";
+ d-cache-line-size = <64>;
+ d-cache-size = <0x10000>;
+ d-cache-sets = <64>;
+ i-cache-line-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <64>;
+ next-level-cache = <&l2_cache_b>;
};
cpu2: cpu@2 {
@@ -95,6 +137,13 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a73";
reg = <0x0 0x2>;
enable-method = "psci";
+ d-cache-line-size = <64>;
+ d-cache-size = <0x10000>;
+ d-cache-sets = <64>;
+ i-cache-line-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <64>;
+ next-level-cache = <&l2_cache_b>;
};
cpu3: cpu@3 {
@@ -102,6 +151,31 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a73";
reg = <0x0 0x3>;
enable-method = "psci";
+ d-cache-line-size = <64>;
+ d-cache-size = <0x10000>;
+ d-cache-sets = <64>;
+ i-cache-line-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <64>;
+ next-level-cache = <&l2_cache_b>;
+ };
+
+ l2_cache_l: l2-cache-cluster0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x40000>; /* L2. 256 KB */
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+
+ l2_cache_b: l2-cache-cluster1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x100000>; /* L2. 1 Mb */
+ cache-line-size = <64>;
+ cache-sets = <512>;
};
};
--
2.50.1
next prev parent reply other threads:[~2025-08-25 7:30 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-25 6:51 [PATCH v2 00/11] Add cache information to Amlogic SoC Anand Moon
2025-08-25 6:51 ` [PATCH v2 01/11] arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC Anand Moon
[not found] ` <19AB5D06-DEB6-4C38-B90D-FCDD9719312C@hewittfamily.org.uk>
2025-08-25 12:57 ` Anand Moon
2025-08-25 6:51 ` [PATCH v2 02/11] arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC Anand Moon
2025-09-04 13:37 ` Krzysztof Kozlowski
2025-09-05 3:51 ` Anand Moon
2025-08-25 6:51 ` [PATCH v2 03/11] arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS Anand Moon
2025-08-25 6:51 ` [PATCH v2 04/11] arm64: dts: amlogic: Add cache information to the Amlogic AXG SoCS Anand Moon
2025-08-25 6:51 ` [PATCH v2 05/11] arm64: dts: amlogic: Add cache information to the Amlogic GXM SoCS Anand Moon
2025-08-25 6:51 ` [PATCH v2 06/11] arm64: dts: amlogic: Add cache information to the Amlogic A1 SoC Anand Moon
2025-08-25 6:51 ` [PATCH v2 07/11] arm64: dts: amlogic: Add cache information to the Amlogic A4 SoC Anand Moon
2025-08-25 6:51 ` [PATCH v2 08/11] arm64: dts: amlogic: Add cache information to the Amlogic C3 SoC Anand Moon
2025-08-25 6:51 ` [PATCH v2 09/11] arm64: dts: amlogic: Add cache information to the Amlogic S7 SoC Anand Moon
2025-08-25 6:51 ` [PATCH v2 10/11] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC Anand Moon
2025-08-25 6:51 ` Anand Moon [this message]
2025-09-04 13:28 ` [PATCH v2 00/11] Add cache information to Amlogic SoC Neil Armstrong
2025-09-05 4:01 ` Anand Moon
2025-09-05 10:20 ` Neil Armstrong
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