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From: Rob Herring <robh@kernel.org>
To: Michael Riesch <michael.riesch@collabora.com>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Heiko Stuebner <heiko@sntech.de>, Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Kever Yang <kever.yang@rock-chips.com>,
	Jagan Teki <jagan@amarulasolutions.com>,
	Sebastian Reichel <sebastian.reichel@collabora.com>,
	Diederik de Haas <didi.debian@cknow.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Collabora Kernel Team <kernel@collabora.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-phy@lists.infradead.org
Subject: Re: [PATCH v2 3/7] dt-bindings: phy: rockchip-inno-csi-dphy: add rk3588 variant
Date: Mon, 25 Aug 2025 17:41:08 -0500	[thread overview]
Message-ID: <20250825224108.GA766877-robh@kernel.org> (raw)
In-Reply-To: <20250616-rk3588-csi-dphy-v2-3-7a94f079b712@collabora.com>

On Tue, Aug 19, 2025 at 01:00:37AM +0200, Michael Riesch wrote:
> The Rockchip RK3588 variant of the CSI-2 DPHY features two reset lines.
> Add the variant and allow for the additional reset.
> 
> Signed-off-by: Michael Riesch <michael.riesch@collabora.com>
> ---
>  .../bindings/phy/rockchip-inno-csi-dphy.yaml       | 60 ++++++++++++++++++++--
>  1 file changed, 56 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml
> index 42da616ae2e3..10197cc9dc47 100644
> --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml
> +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml
> @@ -21,6 +21,7 @@ properties:
>        - rockchip,rk3326-csi-dphy
>        - rockchip,rk3368-csi-dphy
>        - rockchip,rk3568-csi-dphy
> +      - rockchip,rk3588-csi-dphy
>  
>    reg:
>      maxItems: 1
> @@ -39,18 +40,50 @@ properties:
>      maxItems: 1
>  
>    resets:
> -    items:
> -      - description: exclusive PHY reset line
> +    minItems: 1
> +    maxItems: 2

Add a description for the 2nd reset here.

>  
>    reset-names:
> -    items:
> -      - const: apb
> +    minItems: 1
> +    maxItems: 2

Add 'phy' to the list here and just minItems.

>  
>    rockchip,grf:
>      $ref: /schemas/types.yaml#/definitions/phandle
>      description:
>        Some additional phy settings are access through GRF regs.
>  
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - rockchip,px30-csi-dphy
> +              - rockchip,rk1808-csi-dphy
> +              - rockchip,rk3326-csi-dphy
> +              - rockchip,rk3368-csi-dphy
> +              - rockchip,rk3568-csi-dphy
> +    then:
> +      properties:
> +        resets:
> +          items:
> +            - description: exclusive PHY reset line
> +
> +        reset-names:
> +          items:
> +            - const: apb

Then just 'maxItems: 1' here.

> +    else:
> +      properties:
> +        resets:
> +          items:
> +            - description: APB reset line
> +            - description: PHY reset line
> +
> +        reset-names:
> +          items:
> +            - const: apb
> +            - const: phy

And 'minItems: 2' here.

> +
>  required:
>    - compatible
>    - reg
> @@ -77,3 +110,22 @@ examples:
>          reset-names = "apb";
>          rockchip,grf = <&grf>;
>      };
> +  - |
> +    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
> +    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        phy@fedc0000 {
> +            compatible = "rockchip,rk3588-csi-dphy";
> +            reg = <0x0 0xfedc0000 0x0 0x8000>;
> +            clocks = <&cru PCLK_CSIPHY0>;
> +            clock-names = "pclk";
> +            #phy-cells = <0>;
> +            resets = <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>;
> +            reset-names = "apb", "phy";
> +            rockchip,grf = <&csidphy0_grf>;
> +        };
> +    };
> 
> -- 
> 2.39.5
> 


  reply	other threads:[~2025-08-25 22:44 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-18 23:00 [PATCH v2 0/7] phy: rockchip: phy-rockchip-inno-csidphy: add support for rk3588 variant Michael Riesch via B4 Relay
2025-08-18 23:00 ` [PATCH v2 1/7] dt-bindings: soc: rockchip: add rk3588 csidphy grf syscon Michael Riesch via B4 Relay
2025-08-18 23:00 ` [PATCH v2 2/7] dt-bindings: phy: rockchip-inno-csi-dphy: make power-domains non-required Michael Riesch via B4 Relay
2025-08-22  9:33   ` Krzysztof Kozlowski
2025-08-18 23:00 ` [PATCH v2 3/7] dt-bindings: phy: rockchip-inno-csi-dphy: add rk3588 variant Michael Riesch via B4 Relay
2025-08-25 22:41   ` Rob Herring [this message]
2025-08-18 23:00 ` [PATCH v2 4/7] phy: rockchip: phy-rockchip-inno-csidphy: allow writes to grf register 0 Michael Riesch via B4 Relay
2025-08-18 23:00 ` [PATCH v2 5/7] phy: rockchip: phy-rockchip-inno-csidphy: allow for different reset lines Michael Riesch via B4 Relay
2025-08-18 23:00 ` [PATCH v2 6/7] phy: rockchip: phy-rockchip-inno-csidphy: add support for rk3588 variant Michael Riesch via B4 Relay
2025-08-18 23:00 ` [PATCH v2 7/7] arm64: dts: rockchip: add mipi csi-2 dphy nodes to rk3588 Michael Riesch via B4 Relay

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