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[35.233.43.219]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3cc890b178bsm3272069f8f.52.2025.08.27.05.59.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 05:59:50 -0700 (PDT) From: Tudor Ambarus Date: Wed, 27 Aug 2025 12:59:47 +0000 Subject: [PATCH v2 2/3] arm64: dts: exynos: gs101: add CPU clocks MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250827-acpm-dvfs-dt-v2-2-e1d2890d12b4@linaro.org> References: <20250827-acpm-dvfs-dt-v2-0-e1d2890d12b4@linaro.org> In-Reply-To: <20250827-acpm-dvfs-dt-v2-0-e1d2890d12b4@linaro.org> To: Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756299588; l=2740; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=uoqgJ3OhNeN6asyWKYrHarA0VMYib5B/PdW+OT7cv0M=; b=vnVVuPmKG+UU58DxmUVjQUGxPgldzUS4A/j/jb9225yIdT/j7J7EUC0BGjTM1lU6pntynAPaO KdDzTE4di3OCQQZG6n3zIstYLljRQ4YZMRzjMl2OPkxhUs7ftmOMYdd X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250827_055952_850663_611519BC X-CRM114-Status: UNSURE ( 9.41 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the GS101 CPU clocks exposed through the ACPM protocol. Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index f00754692bbac39fd828ebd4ef7c269f746f2522..746b7d8ecdc90fd746015b8322924bac66c6e363 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -72,6 +72,7 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0000>; + clocks = <&acpm_ipc CLK_ACPM_DVFS_CPUCL0>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; @@ -82,6 +83,7 @@ cpu1: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0100>; + clocks = <&acpm_ipc CLK_ACPM_DVFS_CPUCL0>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; @@ -92,6 +94,7 @@ cpu2: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0200>; + clocks = <&acpm_ipc CLK_ACPM_DVFS_CPUCL0>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; @@ -102,6 +105,7 @@ cpu3: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0300>; + clocks = <&acpm_ipc CLK_ACPM_DVFS_CPUCL0>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; @@ -112,6 +116,7 @@ cpu4: cpu@400 { device_type = "cpu"; compatible = "arm,cortex-a76"; reg = <0x0400>; + clocks = <&acpm_ipc CLK_ACPM_DVFS_CPUCL1>; enable-method = "psci"; cpu-idle-states = <&enyo_cpu_sleep>; capacity-dmips-mhz = <620>; @@ -122,6 +127,7 @@ cpu5: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-a76"; reg = <0x0500>; + clocks = <&acpm_ipc CLK_ACPM_DVFS_CPUCL1>; enable-method = "psci"; cpu-idle-states = <&enyo_cpu_sleep>; capacity-dmips-mhz = <620>; @@ -132,6 +138,7 @@ cpu6: cpu@600 { device_type = "cpu"; compatible = "arm,cortex-x1"; reg = <0x0600>; + clocks = <&acpm_ipc CLK_ACPM_DVFS_CPUCL2>; enable-method = "psci"; cpu-idle-states = <&hera_cpu_sleep>; capacity-dmips-mhz = <1024>; @@ -142,6 +149,7 @@ cpu7: cpu@700 { device_type = "cpu"; compatible = "arm,cortex-x1"; reg = <0x0700>; + clocks = <&acpm_ipc CLK_ACPM_DVFS_CPUCL2>; enable-method = "psci"; cpu-idle-states = <&hera_cpu_sleep>; capacity-dmips-mhz = <1024>; -- 2.51.0.261.g7ce5a0a67e-goog