From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38D12CA0EED for ; Thu, 28 Aug 2025 09:07:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ReZvEftY9OCzW7Dm6xWBCAsBP3wLpjVjsHSQsCNwqs8=; b=ihzQS16HAoN2Rheo+95SOzazYl 4gjotxRQg50Hcyb+LTjZazZgF+UM2BAw+A1qZ75OXjvpGliZSsVJyd1glLvuCNbP5w0kRnD9W2fXv +WtkDdM1hgrl2nHMtJPbg5qW1FBH/8dPEjNxNdfarbsx2ntPLgEnVgcNjUm3QaKKOnKUahHZT+AmN NF3q5+RmRVeagn7HZ5iTC3SpeoUAgK+QLhysM5+GC0D7kQ3Y0Pfxa/7gAy1pHejckKG8SFHYfjqHg bZ7gRImCflw4kwFMCnEzPAX8pOUSEVTugUvdNFswMnD6b9/q4qK1nYf5c3QSEeu32+C+TK1S00leI vodUC1HA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1urYbB-00000000udx-0ls9; Thu, 28 Aug 2025 09:07:13 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1urXh7-00000000jTN-2tso; Thu, 28 Aug 2025 08:09:19 +0000 X-UUID: 450b1da483e611f09f706fa2197c6ceb-20250828 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ReZvEftY9OCzW7Dm6xWBCAsBP3wLpjVjsHSQsCNwqs8=; b=Dx7Qk6uN6A9+5AmiRtot0855v6rdTDJp1ZS9gr2KT6pQNAytn84VV9AFtHPLaoWweiaQnfgzvbGcDxWcbh+me6sgWiRAPgdcpWctdeQXU0CHJM5+G+ZpSECIhzQZ92FcjqbhrbzGgYX6qqhqu5lcVfEMIS6wxB/JN0mJcSAJEo8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.3,REQID:5a2729d7-2b28-43ea-96d0-2e78be10e3ba,IP:0,UR L:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:-5 X-CID-META: VersionHash:f1326cf,CLOUDID:35719d7a-966c-41bd-96b5-7d0b3c22e782,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:-5,Content:0|15|50,EDM: -3,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0, AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 450b1da483e611f09f706fa2197c6ceb-20250828 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1208347384; Thu, 28 Aug 2025 01:09:07 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Thu, 28 Aug 2025 16:09:03 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Thu, 28 Aug 2025 16:09:03 +0800 From: Paul Chen To: , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH v4 06/19] soc: mediatek: Add runtime PM and top clocks and async controls for MMSYS Date: Thu, 28 Aug 2025 16:07:01 +0800 Message-ID: <20250828080855.3502514-7-paul-pl.chen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250828080855.3502514-1-paul-pl.chen@mediatek.com> References: <20250828080855.3502514-1-paul-pl.chen@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250828_010917_766979_267423F0 X-CRM114-Status: GOOD ( 20.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Nancy Lin - Add initialization of top clocks and async clocks for each MMSYS. - Add PM runtime control and new functions to manage these clocks. - Add functions to set these clocks according to the default configuration of the corresponding MMSYS. Signed-off-by: Nancy Lin Signed-off-by: Paul-pl Chen --- drivers/soc/mediatek/mtk-mmsys.c | 152 ++++++++++++++++++++++++- drivers/soc/mediatek/mtk-mmsys.h | 18 +++ include/linux/soc/mediatek/mtk-mmsys.h | 8 ++ 3 files changed, 177 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index bb4639ca0b8c..f448cc09ce19 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -4,12 +4,15 @@ * Author: James Liao */ +#include +#include #include #include #include #include #include #include +#include #include #include @@ -158,6 +161,9 @@ struct mtk_mmsys { spinlock_t lock; /* protects mmsys_sw_rst_b reg */ struct reset_controller_dev rcdev; struct cmdq_client_reg cmdq_base; + struct clk **async_clk; + int num_async_clk; + struct clk **top_clk; }; static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val, @@ -180,6 +186,101 @@ static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, writel_relaxed(tmp, mmsys->regs + offset); } +int mtk_mmsys_top_clk_enable(struct device *dev) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + int ret, i; + + if (!mmsys->data->num_top_clk) + return 0; + + for (i = 0; i < mmsys->data->num_top_clk; i++) + ret = clk_prepare_enable(mmsys->top_clk[i]); + return ret; +} +EXPORT_SYMBOL_GPL(mtk_mmsys_top_clk_enable); + +void mtk_mmsys_top_clk_disable(struct device *dev) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + int i; + + for (i = 0; i < mmsys->data->num_top_clk; i++) + clk_disable_unprepare(mmsys->top_clk[i]); +} +EXPORT_SYMBOL_GPL(mtk_mmsys_top_clk_disable); + +int mtk_mmsys_ddp_clk_enable(struct device *dev, enum mtk_ddp_comp_id comp_id) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + const struct mtk_mmsys_async_info *async = mmsys->data->async_info; + + int i; + + if (!mmsys->data->num_async_info) + return 0; + + for (i = 0; i < mmsys->data->num_async_info; i++) + if (comp_id == async[i].comp_id) + return clk_prepare_enable(mmsys->async_clk[async[i].index]); + return 0; +} +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_clk_enable); + +void mtk_mmsys_ddp_clk_disable(struct device *dev, enum mtk_ddp_comp_id comp_id) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + const struct mtk_mmsys_async_info *async = mmsys->data->async_info; + int i; + + if (!mmsys->data->num_async_info) + return; + + for (i = 0; i < mmsys->data->num_async_info; i++) + if (comp_id == async[i].comp_id) + clk_disable_unprepare(mmsys->async_clk[async[i].index]); +} +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_clk_disable); + +void mtk_mmsys_ddp_config(struct device *dev, enum mtk_ddp_comp_id comp_id, + int width, int height, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + const struct mtk_mmsys_async_info *async = mmsys->data->async_info; + int i; + u32 val; + + if (!mmsys->data->num_async_info) + return; + + for (i = 0; i < mmsys->data->num_async_info; i++) + if (comp_id == async[i].comp_id) + break; + + if (i == mmsys->data->num_async_info) + return; + + val = FIELD_PREP(GENMASK(31, 16), height); + val |= FIELD_PREP(GENMASK(15, 0), width); + mtk_mmsys_update_bits(mmsys, async[i].offset, async[i].mask, val, cmdq_pkt); +} +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config); + +void mtk_mmsys_default_config(struct device *dev) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + const struct mtk_mmsys_default *def_config = mmsys->data->def_config; + int i; + + if (!mmsys->data->num_def_config) + return; + + for (i = 0; i < mmsys->data->num_def_config; i++) + mtk_mmsys_update_bits(mmsys, def_config[i].offset, def_config[i].mask, + def_config[i].val, NULL); +} +EXPORT_SYMBOL_GPL(mtk_mmsys_default_config); + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) @@ -390,7 +491,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev) struct platform_device *clks; struct platform_device *drm; struct mtk_mmsys *mmsys; - int ret; + int ret, i; mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); if (!mmsys) @@ -432,6 +533,49 @@ static int mtk_mmsys_probe(struct platform_device *pdev) return PTR_ERR(clks); mmsys->clks_pdev = clks; + if (mmsys->data->num_top_clk) { + struct device_node *node; + + node = of_get_child_by_name(dev->of_node, "top"); + if (!node) { + dev_err(&pdev->dev, "Couldn't find top node\n"); + return -EINVAL; + } + + mmsys->top_clk = devm_kmalloc_array(dev, mmsys->data->num_top_clk, + sizeof(*mmsys->top_clk), GFP_KERNEL); + if (!mmsys->top_clk) + return -ENOMEM; + + for (i = 0; i < mmsys->data->num_top_clk; i++) { + mmsys->top_clk[i] = of_clk_get(node, i); + if (IS_ERR(mmsys->top_clk[i])) + return PTR_ERR(mmsys->top_clk[i]); + } + } + + if (mmsys->data->num_async_info) { + struct device_node *node; + + node = of_get_child_by_name(dev->of_node, "async"); + if (!node) { + dev_err(&pdev->dev, "Couldn't find async node\n"); + return -EINVAL; + } + + mmsys->async_clk = devm_kmalloc_array(dev, mmsys->data->num_async_info, + sizeof(*mmsys->async_clk), GFP_KERNEL); + if (!mmsys->async_clk) + return -ENOMEM; + mmsys->num_async_clk = mmsys->data->num_async_info; + + for (i = 0; i < mmsys->num_async_clk; i++) { + mmsys->async_clk[i] = of_clk_get(node, i); + if (IS_ERR(mmsys->async_clk[i])) + return PTR_ERR(mmsys->async_clk[i]); + } + } + if (mmsys->data->is_vppsys) goto out_probe_done; @@ -443,6 +587,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev) } mmsys->drm_pdev = drm; + if (of_property_present(dev->of_node, "power-domains")) + pm_runtime_enable(dev); + out_probe_done: return 0; } @@ -453,6 +600,9 @@ static void mtk_mmsys_remove(struct platform_device *pdev) platform_device_unregister(mmsys->drm_pdev); platform_device_unregister(mmsys->clks_pdev); + + if (of_property_present(pdev->dev.of_node, "power-domains")) + pm_runtime_disable(&pdev->dev); } static const struct of_device_id of_match_mtk_mmsys[] = { diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index fe628d5f5198..bbc03ef5b025 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -102,6 +102,19 @@ struct mtk_mmsys_routes { u32 val; }; +struct mtk_mmsys_async_info { + u32 comp_id; + u32 index; + u32 offset; + u32 mask; +}; + +struct mtk_mmsys_default { + u32 offset; + u32 val; + u32 mask; +}; + /** * struct mtk_mmsys_driver_data - Settings of the mmsys * @clk_driver: Clock driver name that the mmsys is using @@ -139,6 +152,11 @@ struct mtk_mmsys_driver_data { const u32 num_resets; const bool is_vppsys; const u8 vsync_len; + const struct mtk_mmsys_async_info *async_info; + const unsigned int num_async_info; + const struct mtk_mmsys_default *def_config; + const unsigned int num_def_config; + const unsigned int num_top_clk; }; /* diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 4885b065b849..f50f626e1840 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -84,6 +84,14 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_ID_MAX, }; +int mtk_mmsys_top_clk_enable(struct device *dev); +void mtk_mmsys_top_clk_disable(struct device *dev); +int mtk_mmsys_ddp_clk_enable(struct device *dev, enum mtk_ddp_comp_id comp_id); +void mtk_mmsys_ddp_clk_disable(struct device *dev, enum mtk_ddp_comp_id comp_id); +void mtk_mmsys_ddp_config(struct device *dev, enum mtk_ddp_comp_id comp_id, + int width, int height, struct cmdq_pkt *cmdq_pkt); +void mtk_mmsys_default_config(struct device *dev); + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); -- 2.45.2