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charset=us-ascii Content-Disposition: inline In-Reply-To: <9133348a-f6a4-4425-98e2-a784a7620b3a@foss.st.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250828_101624_718934_EE95A9CA X-CRM114-Status: GOOD ( 25.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Aug 28, 2025 at 02:12:57PM +0200, Christian Bruel wrote: > On 8/27/25 20:58, Bjorn Helgaas wrote: > > On Wed, Aug 20, 2025 at 09:54:06AM +0200, Christian Bruel wrote: > > > Add driver to configure the STM32MP25 SoC PCIe Gen1 2.5GT/s or Gen2 5GT/s > > > controller based on the DesignWare PCIe core in endpoint mode. > > > > > +static void stm32_pcie_perst_deassert(struct dw_pcie *pci) > > > +{ > > > + struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); > > > + struct device *dev = pci->dev; > > > + struct dw_pcie_ep *ep = &pci->ep; > > > + int ret; > > > + > > > + dev_dbg(dev, "PERST de-asserted by host\n"); > > > + > > > + ret = pm_runtime_resume_and_get(dev); > > > + if (ret < 0) { > > > + dev_err(dev, "Failed to resume runtime PM: %d\n", ret); > > > + return; > > > + } > > > + > > > + ret = stm32_pcie_enable_resources(stm32_pcie); > > > + if (ret) { > > > + dev_err(dev, "Failed to enable resources: %d\n", ret); > > > + goto err_pm_put_sync; > > > + } > > > + > > > + /* > > > + * Need to reprogram the configuration space registers here because the > > > + * DBI registers were incorrectly reset by the PHY RCC during phy_init(). > > > > Is this incorrect reset of DBI registers a software issue or some kind > > of hardware erratum that might be fixed someday? Or maybe it's just a > > characteristic of the hardware and thus not really "incorrect"? > > > > I do see that qcom_pcie_perst_deassert() in pcie-qcom-ep.c also calls > > dw_pcie_ep_init_registers() in the qcom_pcie_ep_perst_irq_thread() > > path. > > > > So does pex_ep_event_pex_rst_deassert() (pcie-tegra194.c) in the > > tegra_pcie_ep_pex_rst_irq() path. > > > > But as far as I can tell, none of the other dwc drivers need this, so > > maybe it's something to do with the glue around the DWC core? > > The RCC PHY reset is connected to the Synopsys cold reset logic, which > explains why the registers need to be restored. This point has been > addressed in the reference manual. OK. I dropped "incorrectly" from the comment because I think future readers will wonder about whether or how this could be fixed, and it sounds like it's just a feature of the hardware that we need to deal with. > > > + */ > > > + ret = dw_pcie_ep_init_registers(ep); > > > + if (ret) { > > > + dev_err(dev, "Failed to complete initialization: %d\n", ret); > > > + goto err_disable_resources; > > > + } >