[PATCH v5 00/27] Add support for MT8196 clock controllers

[Laura Nao <laura.nao@collabora.com>]

This patch series introduces support for the clock controllers on the
MediaTek MT8196 platform, following up on an earlier submission[1].

MT8196 uses a hardware voting mechanism to control some of the clock muxes
and gates, along with a fence register responsible for tracking PLL and mux
gate readiness. The series introduces support for these voting and fence
mechanisms, and includes drivers for all clock controllers on the platform.

[1] https://lore.kernel.org/all/20250307032942.10447-1-guangjie.song@mediatek.com/

Changes in v5:
- Used double negation in clk-mux/pll to return strict true/false values
- Dropped fenc_mask from clk-pll.c / clk-pll.h
- Moved MTK_WAIT_FENC_DONE_US definition to clk-mux.c
- Switched to dev_err_probe() / dev_err_ptr_probe() where applicable
- Added blank lines for separation when including binding headers
- Added struct mtk_gate * pointer in struct mtk_clk_gate, removed
  duplication in mtk_clk_register_gate()
- Dropped CLK_OPS_PARENT_ENABLE from gate macros when defining gates
  with different parents
- Used default COMMON_CLK_MT8196 for config COMMON_CLK_MT8196_MDPSYS in
  Kconfig

- Added vlp_clk26m definition in vlpckgen
- Renamed top_divs -> vlp_divs in vlpckgen
- Moved clk-mtk.h inclusion in clk-mux.c to the commit “clk: mediatek:
  clk-mux: Add ops for mux gates with HW voter and FENC”
- Renamed adsppll_ck -> adsppll in topckgen
- Fixed checkpatch warning in clk-mt8196-mdpsys.c (line too long)

- Dropped R-b tags on patches 6 (refactoring), 13 (vlp_clk26m defined,
  reparented audio clocks), 14, 15, 16, 19, 22 (dropped
  CLK_OPS_PARENT_ENABLE, changing the behavior of the
  affected clocks).

Link to v4: https://lore.kernel.org/all/20250805135447.149231-1-laura.nao@collabora.com/

Laura Nao (27):
  clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control
  clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC
  clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and
    FENC
  clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap()
  clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC
  clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use
    mtk_gate struct
  clk: mediatek: clk-gate: Add ops for gates with HW voter
  clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro
  dt-bindings: clock: mediatek: Describe MT8196 clock controllers
  clk: mediatek: Add MT8196 apmixedsys clock support
  clk: mediatek: Add MT8196 topckgen clock support
  clk: mediatek: Add MT8196 topckgen2 clock support
  clk: mediatek: Add MT8196 vlpckgen clock support
  clk: mediatek: Add MT8196 peripheral clock support
  clk: mediatek: Add MT8196 ufssys clock support
  clk: mediatek: Add MT8196 pextpsys clock support
  clk: mediatek: Add MT8196 I2C clock support
  clk: mediatek: Add MT8196 mcu clock support
  clk: mediatek: Add MT8196 mdpsys clock support
  clk: mediatek: Add MT8196 mfg clock support
  clk: mediatek: Add MT8196 disp0 clock support
  clk: mediatek: Add MT8196 disp1 clock support
  clk: mediatek: Add MT8196 disp-ao clock support
  clk: mediatek: Add MT8196 ovl0 clock support
  clk: mediatek: Add MT8196 ovl1 clock support
  clk: mediatek: Add MT8196 vdecsys clock support
  clk: mediatek: Add MT8196 vencsys clock support

 .../bindings/clock/mediatek,mt8196-clock.yaml | 112 ++
 .../clock/mediatek,mt8196-sys-clock.yaml      | 107 ++
 drivers/clk/mediatek/Kconfig                  |  71 ++
 drivers/clk/mediatek/Makefile                 |  13 +
 drivers/clk/mediatek/clk-gate.c               | 119 ++-
 drivers/clk/mediatek/clk-gate.h               |   3 +
 drivers/clk/mediatek/clk-mt8196-apmixedsys.c  | 204 ++++
 drivers/clk/mediatek/clk-mt8196-disp0.c       | 170 +++
 drivers/clk/mediatek/clk-mt8196-disp1.c       | 170 +++
 .../clk/mediatek/clk-mt8196-imp_iic_wrap.c    | 118 +++
 drivers/clk/mediatek/clk-mt8196-mcu.c         | 167 +++
 drivers/clk/mediatek/clk-mt8196-mdpsys.c      | 186 ++++
 drivers/clk/mediatek/clk-mt8196-mfg.c         | 150 +++
 drivers/clk/mediatek/clk-mt8196-ovl0.c        | 154 +++
 drivers/clk/mediatek/clk-mt8196-ovl1.c        | 154 +++
 drivers/clk/mediatek/clk-mt8196-peri_ao.c     | 142 +++
 drivers/clk/mediatek/clk-mt8196-pextp.c       | 131 +++
 drivers/clk/mediatek/clk-mt8196-topckgen.c    | 985 ++++++++++++++++++
 drivers/clk/mediatek/clk-mt8196-topckgen2.c   | 568 ++++++++++
 drivers/clk/mediatek/clk-mt8196-ufs_ao.c      | 108 ++
 drivers/clk/mediatek/clk-mt8196-vdec.c        | 253 +++++
 drivers/clk/mediatek/clk-mt8196-vdisp_ao.c    |  80 ++
 drivers/clk/mediatek/clk-mt8196-venc.c        | 236 +++++
 drivers/clk/mediatek/clk-mt8196-vlpckgen.c    | 729 +++++++++++++
 drivers/clk/mediatek/clk-mtk.c                |  16 +
 drivers/clk/mediatek/clk-mtk.h                |  22 +
 drivers/clk/mediatek/clk-mux.c                | 122 ++-
 drivers/clk/mediatek/clk-mux.h                |  87 ++
 drivers/clk/mediatek/clk-pll.c                |  45 +-
 drivers/clk/mediatek/clk-pll.h                |   8 +
 .../dt-bindings/clock/mediatek,mt8196-clock.h | 803 ++++++++++++++
 .../reset/mediatek,mt8196-resets.h            |  26 +
 32 files changed, 6224 insertions(+), 35 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
 create mode 100644 drivers/clk/mediatek/clk-mt8196-apmixedsys.c
 create mode 100644 drivers/clk/mediatek/clk-mt8196-disp0.c
 create mode 100644 drivers/clk/mediatek/clk-mt8196-disp1.c
 create mode 100644 drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
 create mode 100644 drivers/clk/mediatek/clk-mt8196-mcu.c
 create mode 100644 drivers/clk/mediatek/clk-mt8196-mdpsys.c
 create mode 100644 drivers/clk/mediatek/clk-mt8196-mfg.c
 create mode 100644 drivers/clk/mediatek/clk-mt8196-ovl0.c
 create mode 100644 drivers/clk/mediatek/clk-mt8196-ovl1.c
 create mode 100644 drivers/clk/mediatek/clk-mt8196-peri_ao.c
 create mode 100644 drivers/clk/mediatek/clk-mt8196-pextp.c
 create mode 100644 drivers/clk/mediatek/clk-mt8196-topckgen.c
 create mode 100644 drivers/clk/mediatek/clk-mt8196-topckgen2.c
 create mode 100644 drivers/clk/mediatek/clk-mt8196-ufs_ao.c
 create mode 100644 drivers/clk/mediatek/clk-mt8196-vdec.c
 create mode 100644 drivers/clk/mediatek/clk-mt8196-vdisp_ao.c
 create mode 100644 drivers/clk/mediatek/clk-mt8196-venc.c
 create mode 100644 drivers/clk/mediatek/clk-mt8196-vlpckgen.c
 create mode 100644 include/dt-bindings/clock/mediatek,mt8196-clock.h
 create mode 100644 include/dt-bindings/reset/mediatek,mt8196-resets.h

-- 
2.39.5