* [PATCH v1 1/4] dt-bindings: mfd: aspeed,ast2x00-scu: Support ast2700 pinctrl
2025-08-29 7:30 [PATCH v1 0/4] Add pinctrl support for AST2700 SoC Billy Tsai
@ 2025-08-29 7:30 ` Billy Tsai
2025-08-29 7:30 ` [PATCH v1 2/4] dt-bindings: pinctrl: aspeed: Add support for AST27xx Billy Tsai
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Billy Tsai @ 2025-08-29 7:30 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, joel, andrew, linus.walleij, brgl,
billy_tsai, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel, openbmc, linux-gpio, BMC-SW
Add the ast2700 pinctrl compatible string.
"aspeed,ast2700-soc0-pinctrl" and "aspeed,ast2700-soc1-pinctrl"
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
index 5eccd10d95ce..3a993702a6f6 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
+++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
@@ -61,6 +61,8 @@ patternProperties:
- aspeed,ast2400-pinctrl
- aspeed,ast2500-pinctrl
- aspeed,ast2600-pinctrl
+ - aspeed,ast2700-soc0-pinctrl
+ - aspeed,ast2700-soc1-pinctrl
required:
- compatible
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v1 2/4] dt-bindings: pinctrl: aspeed: Add support for AST27xx
2025-08-29 7:30 [PATCH v1 0/4] Add pinctrl support for AST2700 SoC Billy Tsai
2025-08-29 7:30 ` [PATCH v1 1/4] dt-bindings: mfd: aspeed,ast2x00-scu: Support ast2700 pinctrl Billy Tsai
@ 2025-08-29 7:30 ` Billy Tsai
2025-08-29 13:50 ` Rob Herring (Arm)
2025-08-29 14:24 ` Rob Herring
2025-08-29 7:30 ` [PATCH v1 4/4] arm64: dts: add AST27xx pinctrl configuration nodes Billy Tsai
2025-08-29 14:27 ` [PATCH v1 0/4] Add pinctrl support for AST2700 SoC Rob Herring (Arm)
3 siblings, 2 replies; 7+ messages in thread
From: Billy Tsai @ 2025-08-29 7:30 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, joel, andrew, linus.walleij, brgl,
billy_tsai, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel, openbmc, linux-gpio, BMC-SW
Add bindings for the pin controller found in the ASPEED AST27xx SoC.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
.../pinctrl/aspeed,ast2700-soc0-pinctrl.yaml | 135 ++++++
.../pinctrl/aspeed,ast2700-soc1-pinctrl.yaml | 452 ++++++++++++++++++
2 files changed, 587 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
new file mode 100644
index 000000000000..8abdc2fe1d8b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED AST2700 SoC0 Pin Controller
+
+maintainers:
+ - Billy Tsai <billy_tsai@aspeedtech.com>
+
+description: |+
+ The pin controller node should be the child of a syscon node with the
+ required property:
+
+ - compatible: Should be one of the following:
+ "aspeed,ast2700-scu0", "syscon", "simple-mfd"
+
+ Refer to the bindings described in
+ Documentation/devicetree/bindings/mfd/syscon.yaml
+
+properties:
+ compatible:
+ const: aspeed,ast2700-soc0-pinctrl
+
+additionalProperties:
+ $ref: pinmux-node.yaml#
+ additionalProperties: false
+
+ properties:
+ function:
+ enum:
+ - EMMC
+ - VGADDC
+ - USB3A
+ - USB2A
+ - USB3B
+ - USB2B
+ - JTAG0
+ - PCIERC
+
+ groups:
+ enum:
+ - EMMCG1
+ - EMMCG4
+ - EMMCG8
+ - EMMCWPN
+ - EMMCCDN
+ - VGADDC
+ - USB3AXHD
+ - USB3AXHPD
+ - USB3AXH
+ - USB3AXHP
+ - USB3AXH2B
+ - USB3AXHP2B
+ - USB2AXHD1
+ - USB2AXHPD1
+ - USB2AD1
+ - USB2AXH
+ - USB2AXHP
+ - USB2AXH2B
+ - USB2AXHP2B
+ - USB2AHPD0
+ - USB2AD0
+ - USB2AH
+ - USB2AHP
+ - USB3BXHD
+ - USB3BXHPD
+ - USB3BXH
+ - USB3BXHP
+ - USB3BXH2A
+ - USB3BXHP2A
+ - USB2BXHD1
+ - USB2BXHPD1
+ - USB2BD1
+ - USB2BXH
+ - USB2BXHP
+ - USB2BXH2A
+ - USB2BXHP2A
+ - USB2BHPD0
+ - USB2BD0
+ - USB2BH
+ - USB2BHP
+ - JTAGM0
+ - PSP
+ - SSP
+ - TSP
+ - DDR
+ - USB3A
+ - USB3B
+ - PCIEA
+ - PCIEB
+ - PCIERC0PERST
+ - PCIERC1PERST
+
+ pins: true
+ drive-strength:
+ minimum: 0
+ maximum: 15
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+required:
+ - compatible
+
+examples:
+ - |
+ / {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ syscon0: syscon@12c02000 {
+ compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
+ reg = <0x0 0x12c02000 0x0 0x1000>;
+ ranges = <0x0 0x0 0 0x12c02000 0 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+
+ pinctrl0: pinctrl{
+ compatible = "aspeed,ast2700-soc0-pinctrl";
+
+ pinctrl_emmc_default: emmc-default {
+ function = "EMMC";
+ groups = "EMMCG1";
+ };
+
+ pinctrl_emmcclk_driving: emmcclk-driving {
+ pins = "AC14";
+ drive-strength = <2>;
+ };
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml
new file mode 100644
index 000000000000..1ee71c6290a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml
@@ -0,0 +1,452 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED AST2700 SoC1 Pin Controller
+
+maintainers:
+ - Billy Tsai <billy_tsai@aspeedtech.com>
+
+description: |+
+ The pin controller node should be the child of a syscon node with the
+ required property:
+
+ - compatible: Should be one of the following:
+ "aspeed,ast2700-scu1", "syscon", "simple-mfd"
+
+ Refer to the bindings described in
+ Documentation/devicetree/bindings/mfd/syscon.yaml
+
+properties:
+ compatible:
+ const: aspeed,ast2700-soc1-pinctrl
+
+additionalProperties:
+ $ref: pinmux-node.yaml#
+ additionalProperties: false
+
+ properties:
+ function:
+ enum:
+ - ADC0
+ - ADC1
+ - ADC2
+ - ADC3
+ - ADC4
+ - ADC5
+ - ADC6
+ - ADC7
+ - ADC8
+ - ADC9
+ - ADC10
+ - ADC11
+ - ADC12
+ - ADC13
+ - ADC14
+ - ADC15
+ - CANBUS
+ - DDR
+ - ESPI0
+ - ESPI1
+ - FSI0
+ - FSI1
+ - FSI2
+ - FSI3
+ - FWQSPI
+ - I2C0
+ - I2C1
+ - I2C2
+ - I2C3
+ - I2C4
+ - I2C5
+ - I2C6
+ - I2C7
+ - I2C8
+ - I2C9
+ - I2C10
+ - I2C11
+ - I2C12
+ - I2C13
+ - I2C14
+ - I2C15
+ - I3C0
+ - I3C1
+ - I3C2
+ - I3C3
+ - I3C4
+ - I3C5
+ - I3C6
+ - I3C7
+ - I3C8
+ - I3C9
+ - I3C10
+ - I3C11
+ - I3C12
+ - I3C13
+ - I3C14
+ - I3C15
+ - JTAGM0
+ - JTAGM1
+ - LPC0
+ - LPC1
+ - LTPI_PS_I2C0
+ - LTPI_PS_I2C1
+ - LTPI_PS_I2C2
+ - LTPI_PS_I2C3
+ - MDIO0
+ - MDIO1
+ - MDIO2
+ - NCTS5
+ - NDCD5
+ - NDSR5
+ - NRI5
+ - PCIERC
+ - PWM0
+ - PWM1
+ - PWM2
+ - PWM3
+ - PWM4
+ - PWM5
+ - PWM6
+ - PWM7
+ - PWM8
+ - PWM9
+ - PWM10
+ - PWM11
+ - PWM12
+ - PWM13
+ - PWM14
+ - PWM15
+ - QSPI0
+ - QSPI1
+ - QSPI2
+ - RGMII0
+ - RGMII1
+ - RMII0
+ - RMII0RCLKO
+ - RMII1
+ - RMII1RCLKO
+ - SALT0
+ - SALT1
+ - SALT2
+ - SALT3
+ - SALT4
+ - SALT5
+ - SALT6
+ - SALT7
+ - SALT8
+ - SALT9
+ - SALT10
+ - SALT11
+ - SALT12
+ - SALT13
+ - SALT14
+ - SALT15
+ - SD
+ - SGMII
+ - SGPM0
+ - SGPM1
+ - SGPS
+ - SPI0
+ - SPI0CS1
+ - SPI1
+ - SPI1CS1
+ - SPI2
+ - SPI2CS1
+ - SSP
+ - TACH0
+ - TACH1
+ - TACH2
+ - TACH3
+ - TACH4
+ - TACH5
+ - TACH6
+ - TACH7
+ - TACH8
+ - TACH9
+ - TACH10
+ - TACH11
+ - TACH12
+ - TACH13
+ - TACH14
+ - TACH15
+ - THRU0
+ - THRU1
+ - THRU2
+ - THRU3
+ - TSP
+ - UART0
+ - UART1
+ - UART2
+ - UART3
+ - UART5
+ - UART6
+ - UART7
+ - UART8
+ - UART9
+ - UART10
+ - UART11
+ - USB2C
+ - USB2D
+ - VPI
+
+ groups:
+ enum:
+ - ADC0
+ - ADC1
+ - ADC2
+ - ADC3
+ - ADC4
+ - ADC5
+ - ADC6
+ - ADC7
+ - ADC8
+ - ADC9
+ - ADC10
+ - ADC11
+ - ADC12
+ - ADC13
+ - ADC14
+ - ADC15
+ - CANBUS
+ - DI2C0
+ - DI2C1
+ - DI2C2
+ - DI2C3
+ - DI2C8
+ - DI2C9
+ - DI2C10
+ - DI2C11
+ - DI2C12
+ - DI2C13
+ - DI2C14
+ - DI2C15
+ - DSGPM0
+ - ESPI0
+ - ESPI1
+ - FSI0
+ - FSI1
+ - FSI2
+ - FSI3
+ - FWQSPI
+ - HVI3C0
+ - HVI3C1
+ - HVI3C2
+ - HVI3C3
+ - HVI3C12
+ - HVI3C13
+ - HVI3C14
+ - HVI3C15
+ - I2C0
+ - I2C1
+ - I2C2
+ - I2C3
+ - I2C4
+ - I2C5
+ - I2C6
+ - I2C7
+ - I2C8
+ - I2C9
+ - I2C10
+ - I2C11
+ - I2C12
+ - I2C13
+ - I2C14
+ - I2C15
+ - I3C4
+ - I3C5
+ - I3C6
+ - I3C7
+ - I3C8
+ - I3C9
+ - I3C10
+ - I3C11
+ - JTAGM1
+ - LPC0
+ - LPC1
+ - LTPI_PS_I2C0
+ - LTPI_PS_I2C1
+ - LTPI_PS_I2C2
+ - LTPI_PS_I2C3
+ - MDIO0
+ - MDIO1
+ - MDIO2
+ - NCTS0
+ - NCTS1
+ - NCTS5
+ - NCTS6
+ - NDCD0
+ - NDCD1
+ - NDCD5
+ - NDCD6
+ - NDSR0
+ - NDSR1
+ - NDSR5
+ - NDSR6
+ - NDTR0
+ - NDTR1
+ - NDTR5
+ - NDTR6
+ - NRI0
+ - NRI1
+ - NRI5
+ - NRI6
+ - NRTS0
+ - NRTS1
+ - NRTS5
+ - NRTS6
+ - PE2SGRSTN
+ - PWM0
+ - PWM1
+ - PWM2
+ - PWM3
+ - PWM4
+ - PWM5
+ - PWM6
+ - PWM7
+ - PWM8
+ - PWM9
+ - PWM10
+ - PWM11
+ - PWM12
+ - PWM13
+ - PWM14
+ - PWM15
+ - QSPI0
+ - QSPI1
+ - QSPI2
+ - RGMII0
+ - RGMII1
+ - RMII0
+ - RMII0RCLKO
+ - RMII1
+ - RMII1RCLKO
+ - RXD0
+ - RXD1
+ - RXD2
+ - RXD3
+ - RXD5
+ - RXD6
+ - RXD7
+ - RXD8
+ - RXD9
+ - RXD10
+ - RXD11
+ - SALT0
+ - SALT1
+ - SALT2
+ - SALT3
+ - SALT4
+ - SALT5
+ - SALT6
+ - SALT7
+ - SALT8
+ - SALT9
+ - SALT10
+ - SALT11
+ - SALT12
+ - SALT13
+ - SALT14
+ - SALT15
+ - SD
+ - SGMII
+ - SGPM0
+ - SGPM1
+ - SGPS
+ - SPI0
+ - SPI0CS1
+ - SPI1
+ - SPI1CS1
+ - SPI2
+ - SPI2CS1
+ - TACH0
+ - TACH1
+ - TACH2
+ - TACH3
+ - TACH4
+ - TACH5
+ - TACH6
+ - TACH7
+ - TACH8
+ - TACH9
+ - TACH10
+ - TACH11
+ - TACH12
+ - TACH13
+ - TACH14
+ - TACH15
+ - THRU0
+ - THRU1
+ - THRU2
+ - THRU3
+ - TXD0
+ - TXD1
+ - TXD2
+ - TXD3
+ - TXD5
+ - TXD6
+ - TXD7
+ - TXD8
+ - TXD9
+ - TXD10
+ - TXD11
+ - USB2CD
+ - USB2CH
+ - USB2CU
+ - USB2CUD
+ - USB2DD
+ - USB2DH
+ - VPI
+
+ pins: true
+ bias-disable: true
+ bias-pull-up: true
+ bias-pull-down: true
+ drive-strength:
+ minimum: 0
+ maximum: 3
+ power-source:
+ enum: [1800, 3300]
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+required:
+ - compatible
+
+examples:
+ - |
+ / {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ syscon1: syscon@14c02000 {
+ compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd";
+ reg = <0x0 0x14c02000 0x0 0x1000>;
+ ranges = <0x0 0x0 0x0 0x14c02000 0x0 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+
+ pinctrl1: pinctrl {
+ compatible = "aspeed,ast2700-soc1-pinctrl";
+
+ pinctrl_hvi3c0_default: hvi3c0-default {
+ function = "I3C0";
+ groups = "HVI3C0";
+ };
+
+ pinctrl_i3c0_3_hv_voltage: i3chv-voltage {
+ pins = "U25";
+ power-source = <1800>;
+ };
+
+ pinctrl_i3c0_driving: i3c0-driving {
+ pins = "U25", "U26";
+ drive-strength = <2>;
+ };
+ };
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v1 2/4] dt-bindings: pinctrl: aspeed: Add support for AST27xx
2025-08-29 7:30 ` [PATCH v1 2/4] dt-bindings: pinctrl: aspeed: Add support for AST27xx Billy Tsai
@ 2025-08-29 13:50 ` Rob Herring (Arm)
2025-08-29 14:24 ` Rob Herring
1 sibling, 0 replies; 7+ messages in thread
From: Rob Herring (Arm) @ 2025-08-29 13:50 UTC (permalink / raw)
To: Billy Tsai
Cc: linux-kernel, devicetree, joel, andrew, linux-arm-kernel,
linux-aspeed, linux-gpio, BMC-SW, linus.walleij, lee, krzk+dt,
conor+dt, openbmc, brgl
On Fri, 29 Aug 2025 15:30:28 +0800, Billy Tsai wrote:
> Add bindings for the pin controller found in the ASPEED AST27xx SoC.
>
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> ---
> .../pinctrl/aspeed,ast2700-soc0-pinctrl.yaml | 135 ++++++
> .../pinctrl/aspeed,ast2700-soc1-pinctrl.yaml | 452 ++++++++++++++++++
> 2 files changed, 587 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
> create mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.example.dtb: /: 'compatible' is a required property
from schema $id: http://devicetree.org/schemas/root-node.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.example.dtb: /: 'model' is a required property
from schema $id: http://devicetree.org/schemas/root-node.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.example.dtb: syscon@14c02000 (aspeed,ast2700-scu1): #size-cells: 1 was expected
from schema $id: http://devicetree.org/schemas/mfd/aspeed,ast2x00-scu.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.example.dtb: /: 'compatible' is a required property
from schema $id: http://devicetree.org/schemas/root-node.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.example.dtb: /: 'model' is a required property
from schema $id: http://devicetree.org/schemas/root-node.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.example.dtb: syscon@12c02000 (aspeed,ast2700-scu0): #size-cells: 1 was expected
from schema $id: http://devicetree.org/schemas/mfd/aspeed,ast2x00-scu.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250829073030.2749482-3-billy_tsai@aspeedtech.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1 2/4] dt-bindings: pinctrl: aspeed: Add support for AST27xx
2025-08-29 7:30 ` [PATCH v1 2/4] dt-bindings: pinctrl: aspeed: Add support for AST27xx Billy Tsai
2025-08-29 13:50 ` Rob Herring (Arm)
@ 2025-08-29 14:24 ` Rob Herring
1 sibling, 0 replies; 7+ messages in thread
From: Rob Herring @ 2025-08-29 14:24 UTC (permalink / raw)
To: Billy Tsai
Cc: lee, krzk+dt, conor+dt, joel, andrew, linus.walleij, brgl,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, openbmc,
linux-gpio, BMC-SW
On Fri, Aug 29, 2025 at 03:30:28PM +0800, Billy Tsai wrote:
> Add bindings for the pin controller found in the ASPEED AST27xx SoC.
Please explain why you have defined 2 pin controllers and why they
aren't compatible with each other.
>
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> ---
> .../pinctrl/aspeed,ast2700-soc0-pinctrl.yaml | 135 ++++++
> .../pinctrl/aspeed,ast2700-soc1-pinctrl.yaml | 452 ++++++++++++++++++
> 2 files changed, 587 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
> create mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
> new file mode 100644
> index 000000000000..8abdc2fe1d8b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
> @@ -0,0 +1,135 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ASPEED AST2700 SoC0 Pin Controller
> +
> +maintainers:
> + - Billy Tsai <billy_tsai@aspeedtech.com>
> +
> +description: |+
What's the '+' for?
> + The pin controller node should be the child of a syscon node with the
> + required property:
> +
> + - compatible: Should be one of the following:
> + "aspeed,ast2700-scu0", "syscon", "simple-mfd"
This should be a schema in the aspeed,ast2700-scu0 binding, not a
free-form text description.
> +
> + Refer to the bindings described in
> + Documentation/devicetree/bindings/mfd/syscon.yaml
That does not cover 'simple-mfd' cases.
> +
> +properties:
> + compatible:
> + const: aspeed,ast2700-soc0-pinctrl
> +
> +additionalProperties:
> + $ref: pinmux-node.yaml#
> + additionalProperties: false
> +
> + properties:
> + function:
> + enum:
> + - EMMC
> + - VGADDC
> + - USB3A
> + - USB2A
> + - USB3B
> + - USB2B
> + - JTAG0
> + - PCIERC
> +
> + groups:
> + enum:
> + - EMMCG1
> + - EMMCG4
> + - EMMCG8
> + - EMMCWPN
> + - EMMCCDN
> + - VGADDC
> + - USB3AXHD
> + - USB3AXHPD
> + - USB3AXH
> + - USB3AXHP
> + - USB3AXH2B
> + - USB3AXHP2B
> + - USB2AXHD1
> + - USB2AXHPD1
> + - USB2AD1
> + - USB2AXH
> + - USB2AXHP
> + - USB2AXH2B
> + - USB2AXHP2B
> + - USB2AHPD0
> + - USB2AD0
> + - USB2AH
> + - USB2AHP
> + - USB3BXHD
> + - USB3BXHPD
> + - USB3BXH
> + - USB3BXHP
> + - USB3BXH2A
> + - USB3BXHP2A
> + - USB2BXHD1
> + - USB2BXHPD1
> + - USB2BD1
> + - USB2BXH
> + - USB2BXHP
> + - USB2BXH2A
> + - USB2BXHP2A
> + - USB2BHPD0
> + - USB2BD0
> + - USB2BH
> + - USB2BHP
> + - JTAGM0
> + - PSP
> + - SSP
> + - TSP
> + - DDR
> + - USB3A
> + - USB3B
> + - PCIEA
> + - PCIEB
> + - PCIERC0PERST
> + - PCIERC1PERST
> +
> + pins: true
You need to define the type as string or uint32 is possible.
> + drive-strength:
> + minimum: 0
> + maximum: 15
> +
> +allOf:
> + - $ref: pinctrl.yaml#
> +
> +required:
> + - compatible
> +
> +examples:
> + - |
> + / {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + syscon0: syscon@12c02000 {
> + compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
Drop the example here and put a complete example in the schema for the
syscon.
> + reg = <0x0 0x12c02000 0x0 0x1000>;
> + ranges = <0x0 0x0 0 0x12c02000 0 0x1000>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> +
> + pinctrl0: pinctrl{
> + compatible = "aspeed,ast2700-soc0-pinctrl";
> +
> + pinctrl_emmc_default: emmc-default {
> + function = "EMMC";
> + groups = "EMMCG1";
> + };
> +
> + pinctrl_emmcclk_driving: emmcclk-driving {
> + pins = "AC14";
> + drive-strength = <2>;
> + };
> + };
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml
> new file mode 100644
> index 000000000000..1ee71c6290a6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml
> @@ -0,0 +1,452 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ASPEED AST2700 SoC1 Pin Controller
> +
> +maintainers:
> + - Billy Tsai <billy_tsai@aspeedtech.com>
> +
> +description: |+
> + The pin controller node should be the child of a syscon node with the
> + required property:
> +
> + - compatible: Should be one of the following:
> + "aspeed,ast2700-scu1", "syscon", "simple-mfd"
> +
> + Refer to the bindings described in
> + Documentation/devicetree/bindings/mfd/syscon.yaml
> +
> +properties:
> + compatible:
> + const: aspeed,ast2700-soc1-pinctrl
> +
> +additionalProperties:
> + $ref: pinmux-node.yaml#
> + additionalProperties: false
> +
> + properties:
> + function:
> + enum:
> + - ADC0
> + - ADC1
> + - ADC2
> + - ADC3
> + - ADC4
> + - ADC5
> + - ADC6
> + - ADC7
> + - ADC8
> + - ADC9
> + - ADC10
> + - ADC11
> + - ADC12
> + - ADC13
> + - ADC14
> + - ADC15
> + - CANBUS
> + - DDR
> + - ESPI0
> + - ESPI1
> + - FSI0
> + - FSI1
> + - FSI2
> + - FSI3
> + - FWQSPI
> + - I2C0
> + - I2C1
> + - I2C2
> + - I2C3
> + - I2C4
> + - I2C5
> + - I2C6
> + - I2C7
> + - I2C8
> + - I2C9
> + - I2C10
> + - I2C11
> + - I2C12
> + - I2C13
> + - I2C14
> + - I2C15
> + - I3C0
> + - I3C1
> + - I3C2
> + - I3C3
> + - I3C4
> + - I3C5
> + - I3C6
> + - I3C7
> + - I3C8
> + - I3C9
> + - I3C10
> + - I3C11
> + - I3C12
> + - I3C13
> + - I3C14
> + - I3C15
> + - JTAGM0
> + - JTAGM1
> + - LPC0
> + - LPC1
> + - LTPI_PS_I2C0
> + - LTPI_PS_I2C1
> + - LTPI_PS_I2C2
> + - LTPI_PS_I2C3
> + - MDIO0
> + - MDIO1
> + - MDIO2
> + - NCTS5
> + - NDCD5
> + - NDSR5
> + - NRI5
> + - PCIERC
> + - PWM0
> + - PWM1
> + - PWM2
> + - PWM3
> + - PWM4
> + - PWM5
> + - PWM6
> + - PWM7
> + - PWM8
> + - PWM9
> + - PWM10
> + - PWM11
> + - PWM12
> + - PWM13
> + - PWM14
> + - PWM15
> + - QSPI0
> + - QSPI1
> + - QSPI2
> + - RGMII0
> + - RGMII1
> + - RMII0
> + - RMII0RCLKO
> + - RMII1
> + - RMII1RCLKO
> + - SALT0
> + - SALT1
> + - SALT2
> + - SALT3
> + - SALT4
> + - SALT5
> + - SALT6
> + - SALT7
> + - SALT8
> + - SALT9
> + - SALT10
> + - SALT11
> + - SALT12
> + - SALT13
> + - SALT14
> + - SALT15
> + - SD
> + - SGMII
> + - SGPM0
> + - SGPM1
> + - SGPS
> + - SPI0
> + - SPI0CS1
> + - SPI1
> + - SPI1CS1
> + - SPI2
> + - SPI2CS1
> + - SSP
> + - TACH0
> + - TACH1
> + - TACH2
> + - TACH3
> + - TACH4
> + - TACH5
> + - TACH6
> + - TACH7
> + - TACH8
> + - TACH9
> + - TACH10
> + - TACH11
> + - TACH12
> + - TACH13
> + - TACH14
> + - TACH15
> + - THRU0
> + - THRU1
> + - THRU2
> + - THRU3
> + - TSP
> + - UART0
> + - UART1
> + - UART2
> + - UART3
> + - UART5
> + - UART6
> + - UART7
> + - UART8
> + - UART9
> + - UART10
> + - UART11
> + - USB2C
> + - USB2D
> + - VPI
> +
> + groups:
> + enum:
> + - ADC0
> + - ADC1
> + - ADC2
> + - ADC3
> + - ADC4
> + - ADC5
> + - ADC6
> + - ADC7
> + - ADC8
> + - ADC9
> + - ADC10
> + - ADC11
> + - ADC12
> + - ADC13
> + - ADC14
> + - ADC15
> + - CANBUS
> + - DI2C0
> + - DI2C1
> + - DI2C2
> + - DI2C3
> + - DI2C8
> + - DI2C9
> + - DI2C10
> + - DI2C11
> + - DI2C12
> + - DI2C13
> + - DI2C14
> + - DI2C15
> + - DSGPM0
> + - ESPI0
> + - ESPI1
> + - FSI0
> + - FSI1
> + - FSI2
> + - FSI3
> + - FWQSPI
> + - HVI3C0
> + - HVI3C1
> + - HVI3C2
> + - HVI3C3
> + - HVI3C12
> + - HVI3C13
> + - HVI3C14
> + - HVI3C15
> + - I2C0
> + - I2C1
> + - I2C2
> + - I2C3
> + - I2C4
> + - I2C5
> + - I2C6
> + - I2C7
> + - I2C8
> + - I2C9
> + - I2C10
> + - I2C11
> + - I2C12
> + - I2C13
> + - I2C14
> + - I2C15
> + - I3C4
> + - I3C5
> + - I3C6
> + - I3C7
> + - I3C8
> + - I3C9
> + - I3C10
> + - I3C11
> + - JTAGM1
> + - LPC0
> + - LPC1
> + - LTPI_PS_I2C0
> + - LTPI_PS_I2C1
> + - LTPI_PS_I2C2
> + - LTPI_PS_I2C3
> + - MDIO0
> + - MDIO1
> + - MDIO2
> + - NCTS0
> + - NCTS1
> + - NCTS5
> + - NCTS6
> + - NDCD0
> + - NDCD1
> + - NDCD5
> + - NDCD6
> + - NDSR0
> + - NDSR1
> + - NDSR5
> + - NDSR6
> + - NDTR0
> + - NDTR1
> + - NDTR5
> + - NDTR6
> + - NRI0
> + - NRI1
> + - NRI5
> + - NRI6
> + - NRTS0
> + - NRTS1
> + - NRTS5
> + - NRTS6
> + - PE2SGRSTN
> + - PWM0
> + - PWM1
> + - PWM2
> + - PWM3
> + - PWM4
> + - PWM5
> + - PWM6
> + - PWM7
> + - PWM8
> + - PWM9
> + - PWM10
> + - PWM11
> + - PWM12
> + - PWM13
> + - PWM14
> + - PWM15
> + - QSPI0
> + - QSPI1
> + - QSPI2
> + - RGMII0
> + - RGMII1
> + - RMII0
> + - RMII0RCLKO
> + - RMII1
> + - RMII1RCLKO
> + - RXD0
> + - RXD1
> + - RXD2
> + - RXD3
> + - RXD5
> + - RXD6
> + - RXD7
> + - RXD8
> + - RXD9
> + - RXD10
> + - RXD11
> + - SALT0
> + - SALT1
> + - SALT2
> + - SALT3
> + - SALT4
> + - SALT5
> + - SALT6
> + - SALT7
> + - SALT8
> + - SALT9
> + - SALT10
> + - SALT11
> + - SALT12
> + - SALT13
> + - SALT14
> + - SALT15
> + - SD
> + - SGMII
> + - SGPM0
> + - SGPM1
> + - SGPS
> + - SPI0
> + - SPI0CS1
> + - SPI1
> + - SPI1CS1
> + - SPI2
> + - SPI2CS1
> + - TACH0
> + - TACH1
> + - TACH2
> + - TACH3
> + - TACH4
> + - TACH5
> + - TACH6
> + - TACH7
> + - TACH8
> + - TACH9
> + - TACH10
> + - TACH11
> + - TACH12
> + - TACH13
> + - TACH14
> + - TACH15
> + - THRU0
> + - THRU1
> + - THRU2
> + - THRU3
> + - TXD0
> + - TXD1
> + - TXD2
> + - TXD3
> + - TXD5
> + - TXD6
> + - TXD7
> + - TXD8
> + - TXD9
> + - TXD10
> + - TXD11
> + - USB2CD
> + - USB2CH
> + - USB2CU
> + - USB2CUD
> + - USB2DD
> + - USB2DH
> + - VPI
> +
> + pins: true
> + bias-disable: true
> + bias-pull-up: true
> + bias-pull-down: true
> + drive-strength:
> + minimum: 0
> + maximum: 3
> + power-source:
> + enum: [1800, 3300]
> +
> +allOf:
> + - $ref: pinctrl.yaml#
> +
> +required:
> + - compatible
> +
> +examples:
> + - |
> + / {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + syscon1: syscon@14c02000 {
> + compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd";
> + reg = <0x0 0x14c02000 0x0 0x1000>;
> + ranges = <0x0 0x0 0x0 0x14c02000 0x0 0x1000>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> +
> + pinctrl1: pinctrl {
> + compatible = "aspeed,ast2700-soc1-pinctrl";
> +
> + pinctrl_hvi3c0_default: hvi3c0-default {
> + function = "I3C0";
> + groups = "HVI3C0";
> + };
> +
> + pinctrl_i3c0_3_hv_voltage: i3chv-voltage {
> + pins = "U25";
> + power-source = <1800>;
> + };
> +
> + pinctrl_i3c0_driving: i3c0-driving {
> + pins = "U25", "U26";
> + drive-strength = <2>;
> + };
> + };
> + };
> + };
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v1 4/4] arm64: dts: add AST27xx pinctrl configuration nodes
2025-08-29 7:30 [PATCH v1 0/4] Add pinctrl support for AST2700 SoC Billy Tsai
2025-08-29 7:30 ` [PATCH v1 1/4] dt-bindings: mfd: aspeed,ast2x00-scu: Support ast2700 pinctrl Billy Tsai
2025-08-29 7:30 ` [PATCH v1 2/4] dt-bindings: pinctrl: aspeed: Add support for AST27xx Billy Tsai
@ 2025-08-29 7:30 ` Billy Tsai
2025-08-29 14:27 ` [PATCH v1 0/4] Add pinctrl support for AST2700 SoC Rob Herring (Arm)
3 siblings, 0 replies; 7+ messages in thread
From: Billy Tsai @ 2025-08-29 7:30 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, joel, andrew, linus.walleij, brgl,
billy_tsai, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel, openbmc, linux-gpio, BMC-SW
Add pinctrl0 and pinctrl1 nodes for AST27xx SoC0 and SoC1 to configure
the pinmux settings for each ball.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
.../boot/dts/aspeed/aspeed-g7-pinctrl.dtsi | 1359 +++++++++++++++++
1 file changed, 1359 insertions(+)
create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7-pinctrl.dtsi
diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7-pinctrl.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7-pinctrl.dtsi
new file mode 100644
index 000000000000..2167db85839d
--- /dev/null
+++ b/arch/arm64/boot/dts/aspeed/aspeed-g7-pinctrl.dtsi
@@ -0,0 +1,1359 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2025 ASPEED Corp.
+
+&pinctrl0 {
+ pinctrl_emmc_default: emmc-default {
+ function = "EMMC";
+ groups = "EMMCG1";
+ };
+
+ pinctrl_emmcg4_default: emmc-default {
+ function = "EMMC";
+ groups = "EMMCG4";
+ };
+
+ pinctrl_emmcg8_default: emmcg8-default {
+ function = "EMMC";
+ groups = "EMMCG8";
+ };
+
+ pinctrl_emmcwpn_default: emmcwpn-default {
+ function = "EMMC";
+ groups = "EMMCWPN";
+ };
+
+ pinctrl_emmccdn_default: emmccdn-default {
+ function = "EMMC";
+ groups = "EMMCCDN";
+ };
+
+ pinctrl_vgaddc_default: vgaddc-default {
+ function = "VGADDC";
+ groups = "VGADDC";
+ };
+
+ pinctrl_usb3axhd_default: usb3axhd-default {
+ function = "USB3A";
+ groups = "USB3AXHD";
+ };
+
+ pinctrl_usb3axhpd_default: usb3axhpd-default {
+ function = "USB3A";
+ groups = "USB3AXHPD";
+ };
+
+ pinctrl_usb3axh_default: usb3axh-default {
+ function = "USB3A";
+ groups = "USB3AXH";
+ };
+
+ pinctrl_usb3axhp_default: usb3axhp-default {
+ function = "USB3A";
+ groups = "USB3AXHP";
+ };
+
+ pinctrl_usb3axh2b_default: usb3axh2b-default {
+ function = "USB3A";
+ groups = "USB3AXH2B";
+ };
+
+ pinctrl_usb3axhp2b_default: usb3axhp2b-default {
+ function = "USB3A";
+ groups = "USB3AXHP2B";
+ };
+
+ pinctrl_usb2axhd1_default: usb2axhd1-default {
+ function = "USB2A";
+ groups = "USB2AXHD1";
+ };
+
+ pinctrl_usb2axhpd1_default: usb2axhpd1-default {
+ function = "USB2A";
+ groups = "USB2AXHPD1";
+ };
+
+ pinctrl_usb2ad1_default: usb2ad1-default {
+ function = "USB2A";
+ groups = "USB2AD1";
+ };
+
+ pinctrl_usb2axh_default: usb2axh-default {
+ function = "USB2A";
+ groups = "USB2AXH";
+ };
+
+ pinctrl_usb2axhp_default: usb2axhp-default {
+ function = "USB2A";
+ groups = "USB2AXHP";
+ };
+
+ pinctrl_usb2axh2b_default: usb2axh2b-default {
+ function = "USB2A";
+ groups = "USB2AXH2B";
+ };
+
+ pinctrl_usb2axhp2b_default: usb2axhp2b-default {
+ function = "USB2A";
+ groups = "USB2AXHP2B";
+ };
+
+ pinctrl_usb2ahpd0_default: usb2ahpd0-default {
+ function = "USB2A";
+ groups = "USB2AHPD0";
+ };
+
+ pinctrl_usb2ad0_default: usb2ad0-default {
+ function = "USB2A";
+ groups = "USB2AD0";
+ };
+
+ pinctrl_usb2ah_default: usb2ah-default {
+ function = "USB2A";
+ groups = "USB2AH";
+ };
+
+ pinctrl_usb2ahp_default: usb2ahp-default {
+ function = "USB2A";
+ groups = "USB2AHP";
+ };
+
+ pinctrl_usb3bxhd_default: usb3bxhd-default {
+ function = "USB3B";
+ groups = "USB3BXHD";
+ };
+
+ pinctrl_usb3bxhpd_default: usb3bxhpd-default {
+ function = "USB3B";
+ groups = "USB3BXHPD";
+ };
+
+ pinctrl_usb3bxh_default: usb3bxh-default {
+ function = "USB3B";
+ groups = "USB3BXH";
+ };
+
+ pinctrl_usb3bxhp_default: usb3bxhp-default {
+ function = "USB3B";
+ groups = "USB3BXHP";
+ };
+
+ pinctrl_usb3bxh2a_default: usb3bxh2a-default {
+ function = "USB3B";
+ groups = "USB3BXH2A";
+ };
+
+ pinctrl_usb3bxhp2a_default: usb3bxhp2a-default {
+ function = "USB3B";
+ groups = "USB3BXHP2A";
+ };
+
+ pinctrl_usb2bxhd1_default: usb2bxhd1-default {
+ function = "USB2B";
+ groups = "USB2BXHD1";
+ };
+
+ pinctrl_usb2bxhpd1_default: usb2bxhpd1-default {
+ function = "USB2B";
+ groups = "USB2BXHPD1";
+ };
+
+ pinctrl_usb2bd1_default: usb2bd1-default {
+ function = "USB2B";
+ groups = "USB2BD1";
+ };
+
+ pinctrl_usb2bxh_default: usb2bxh-default {
+ function = "USB2B";
+ groups = "USB2BXH";
+ };
+
+ pinctrl_usb2bxhp_default: usb2bxhp-default {
+ function = "USB2B";
+ groups = "USB2BXHP";
+ };
+
+ pinctrl_usb2bxh2a_default: usb2bxh2a-default {
+ function = "USB2B";
+ groups = "USB2BXH2A";
+ };
+
+ pinctrl_usb2bxhp2a_default: usb2bxhp2a-default {
+ function = "USB2B";
+ groups = "USB2BXHP2A";
+ };
+
+ pinctrl_usb2bhpd0_default: usb2bhpd0-default {
+ function = "USB2B";
+ groups = "USB2BHPD0";
+ };
+
+ pinctrl_usb2bd0_default: usb2bd0-default {
+ function = "USB2B";
+ groups = "USB2BD0";
+ };
+
+ pinctrl_usb2bh_default: usb2bh-default {
+ function = "USB2B";
+ groups = "USB2BH";
+ };
+
+ pinctrl_usb2bhp_default: usb2bhp-default {
+ function = "USB2B";
+ groups = "USB2BHP";
+ };
+
+ pinctrl_jtagm0_default: jtagm0-default {
+ function = "JTAG0";
+ groups = "JTAGM0";
+ };
+
+ pinctrl_jtag_psp_default: jtag-psp-default {
+ function = "JTAG0";
+ groups = "PSP";
+ };
+
+ pinctrl_jtag_ssp_default: jtag-ssp-default {
+ function = "JTAG0";
+ groups = "SSP";
+ };
+
+ pinctrl_jtag_tsp_default: jtag-tsp-default {
+ function = "JTAG0";
+ groups = "TSP";
+ };
+
+ pinctrl_jtag_ddr_default: jtag-ddr-default {
+ function = "JTAG0";
+ groups = "DDR";
+ };
+
+ pinctrl_jtag_usb3a_default: jtag-usb3a-default {
+ function = "JTAG0";
+ groups = "USB3A";
+ };
+
+ pinctrl_jtag_usb3b_default: jtag-usb3b-default {
+ function = "JTAG0";
+ groups = "USB3B";
+ };
+
+ pinctrl_jtag_pciea_default: jtag-pciea-default {
+ function = "JTAG0";
+ groups = "PCIEA";
+ };
+
+ pinctrl_jtag_pcieb_default: jtag-pcieb-default {
+ function = "JTAG0";
+ groups = "PCIEB";
+ };
+
+ pinctrl_pcierc0_perst_default: pcierc0-perst-default {
+ function = "PCIERC";
+ groups = "PCIERC0PERST";
+ };
+
+ pinctrl_pcierc1_perst_default: pcierc1-perst-default {
+ function = "PCIERC";
+ groups = "PCIERC1PERST";
+ };
+};
+
+&pinctrl1 {
+ pinctrl_sgpm0_default: sgpm0-default {
+ function = "SGPM0";
+ groups = "SGPM0";
+ };
+
+ pinctrl_sgpm1_default: sgpm1-default {
+ function = "SGPM1";
+ groups = "SGPM1";
+ };
+
+ pinctrl_sgps_default: sgps-default {
+ function = "SGPS";
+ groups = "SGPS";
+ };
+
+ pinctrl_adc0_default: adc0-default {
+ function = "ADC0";
+ groups = "ADC0";
+ };
+
+ pinctrl_adc1_default: adc1-default {
+ function = "ADC1";
+ groups = "ADC1";
+ };
+
+ pinctrl_adc2_default: adc2-default {
+ function = "ADC2";
+ groups = "ADC2";
+ };
+
+ pinctrl_adc3_default: adc3-default {
+ function = "ADC3";
+ groups = "ADC3";
+ };
+
+ pinctrl_adc4_default: adc4-default {
+ function = "ADC4";
+ groups = "ADC4";
+ };
+
+ pinctrl_adc5_default: adc5-default {
+ function = "ADC5";
+ groups = "ADC5";
+ };
+
+ pinctrl_adc6_default: adc6-default {
+ function = "ADC6";
+ groups = "ADC6";
+ };
+
+ pinctrl_adc7_default: adc7-default {
+ function = "ADC7";
+ groups = "ADC7";
+ };
+
+ pinctrl_adc8_default: adc8-default {
+ function = "ADC8";
+ groups = "ADC8";
+ };
+
+ pinctrl_adc9_default: adc9-default {
+ function = "ADC9";
+ groups = "ADC9";
+ };
+
+ pinctrl_adc10_default: adc10-default {
+ function = "ADC10";
+ groups = "ADC10";
+ };
+
+ pinctrl_adc11_default: adc11-default {
+ function = "ADC11";
+ groups = "ADC11";
+ };
+
+ pinctrl_adc12_default: adc12-default {
+ function = "ADC12";
+ groups = "ADC12";
+ };
+
+ pinctrl_adc13_default: adc13-default {
+ function = "ADC13";
+ groups = "ADC13";
+ };
+
+ pinctrl_adc14_default: adc14-default {
+ function = "ADC14";
+ groups = "ADC14";
+ };
+
+ pinctrl_adc15_default: adc15-default {
+ function = "ADC15";
+ groups = "ADC15";
+ };
+
+ pinctrl_pwm0_default: pwm0-default {
+ function = "PWM0";
+ groups = "PWM0";
+ };
+
+ pinctrl_pwm1_default: pwm1-default {
+ function = "PWM1";
+ groups = "PWM1";
+ };
+
+ pinctrl_pwm2_default: pwm2-default {
+ function = "PWM2";
+ groups = "PWM2";
+ };
+
+ pinctrl_pwm3_default: pwm3-default {
+ function = "PWM3";
+ groups = "PWM3";
+ };
+
+ pinctrl_pwm4_default: pwm4-default {
+ function = "PWM4";
+ groups = "PWM4";
+ };
+
+ pinctrl_pwm5_default: pwm5-default {
+ function = "PWM5";
+ groups = "PWM5";
+ };
+
+ pinctrl_pwm6_default: pwm6-default {
+ function = "PWM6";
+ groups = "PWM6";
+ };
+
+ pinctrl_pwm7_default: pwm7-default {
+ function = "PWM7";
+ groups = "PWM7";
+ };
+
+ pinctrl_pwm8_default: pwm8-default {
+ function = "PWM8";
+ groups = "PWM8";
+ };
+
+ pinctrl_pwm9_default: pwm9-default {
+ function = "PWM9";
+ groups = "PWM9";
+ };
+
+ pinctrl_pwm10_default: pwm10-default {
+ function = "PWM10";
+ groups = "PWM10";
+ };
+
+ pinctrl_pwm11_default: pwm11-default {
+ function = "PWM11";
+ groups = "PWM11";
+ };
+
+ pinctrl_pwm12_default: pwm12-default {
+ function = "PWM12";
+ groups = "PWM12";
+ };
+
+ pinctrl_pwm13_default: pwm13-default {
+ function = "PWM13";
+ groups = "PWM13";
+ };
+
+ pinctrl_pwm14_default: pwm14-default {
+ function = "PWM14";
+ groups = "PWM14";
+ };
+
+ pinctrl_pwm15_default: pwm15-default {
+ function = "PWM15";
+ groups = "PWM15";
+ };
+
+ pinctrl_tach0_default: tach0-default {
+ function = "TACH0";
+ groups = "TACH0";
+ };
+
+ pinctrl_tach1_default: tach1-default {
+ function = "TACH1";
+ groups = "TACH1";
+ };
+
+ pinctrl_tach2_default: tach2-default {
+ function = "TACH2";
+ groups = "TACH2";
+ };
+
+ pinctrl_tach3_default: tach3-default {
+ function = "TACH3";
+ groups = "TACH3";
+ };
+
+ pinctrl_tach4_default: tach4-default {
+ function = "TACH4";
+ groups = "TACH4";
+ };
+
+ pinctrl_tach5_default: tach5-default {
+ function = "TACH5";
+ groups = "TACH5";
+ };
+
+ pinctrl_tach6_default: tach6-default {
+ function = "TACH6";
+ groups = "TACH6";
+ };
+
+ pinctrl_tach7_default: tach7-default {
+ function = "TACH7";
+ groups = "TACH7";
+ };
+
+ pinctrl_tach8_default: tach8-default {
+ function = "TACH8";
+ groups = "TACH8";
+ };
+
+ pinctrl_tach9_default: tach9-default {
+ function = "TACH9";
+ groups = "TACH9";
+ };
+
+ pinctrl_tach10_default: tach10-default {
+ function = "TACH10";
+ groups = "TACH10";
+ };
+
+ pinctrl_tach11_default: tach11-default {
+ function = "TACH11";
+ groups = "TACH11";
+ };
+
+ pinctrl_tach12_default: tach12-default {
+ function = "TACH12";
+ groups = "TACH12";
+ };
+
+ pinctrl_tach13_default: tach13-default {
+ function = "TACH13";
+ groups = "TACH13";
+ };
+
+ pinctrl_tach14_default: tach14-default {
+ function = "TACH14";
+ groups = "TACH14";
+ };
+
+ pinctrl_tach15_default: tach15-default {
+ function = "TACH15";
+ groups = "TACH15";
+ };
+
+ pinctrl_jtagm1_default: jtagm1-default {
+ function = "JTAGM1";
+ groups = "JTAGM1";
+ };
+
+ pinctrl_mdio0_default: mdio0-default {
+ function = "MDIO0";
+ groups = "MDIO0";
+ };
+
+ pinctrl_mdio1_default: mdio1-default {
+ function = "MDIO1";
+ groups = "MDIO1";
+ };
+
+ pinctrl_mdio2_default: mdio2-default {
+ function = "MDIO2";
+ groups = "MDIO2";
+ };
+
+ pinctrl_rgmii0_default: rgmii0-default {
+ function = "RGMII0";
+ groups = "RGMII0";
+ };
+
+ pinctrl_rgmii1_default: rgmii1-default {
+ function = "RGMII1";
+ groups = "RGMII1";
+ };
+
+ pinctrl_rmii0_default: rmii0-default {
+ function = "RMII0";
+ groups = "RMII0";
+ };
+
+ pinctrl_rmii0_rclko_default: rmii0-rclko-default {
+ function = "RMII0RCLKO";
+ groups = "RMII0RCLKO";
+ };
+
+ pinctrl_rmii1_default: rmii1-default {
+ function = "RMII1";
+ groups = "RMII1";
+ };
+
+ pinctrl_rmii1_rclko_default: rmii1-rclko-default {
+ function = "RMII1RCLKO";
+ groups = "RMII1RCLKO";
+ };
+
+ pinctrl_sgmii_default: sgmii-default {
+ function = "SGMII";
+ groups = "SGMII";
+ };
+
+ pinctrl_fwspi_quad_default: fwspi-quad-default {
+ function = "FWQSPI";
+ groups = "FWQSPI";
+ };
+
+ pinctrl_fsi0_default: fsi0-default {
+ function = "FSI0";
+ groups = "FSI0";
+ };
+
+ pinctrl_fsi1_default: fsi1-default {
+ function = "FSI1";
+ groups = "FSI1";
+ };
+
+ pinctrl_fsi2_default: fsi2-default {
+ function = "FSI2";
+ groups = "FSI2";
+ };
+
+ pinctrl_fsi3_default: fsi3-default {
+ function = "FSI3";
+ groups = "FSI3";
+ };
+
+ pinctrl_spi0_default: spi0-default {
+ function = "SPI0";
+ groups = "SPI0";
+ };
+
+ pinctrl_spi0_quad_default: spi0-quad-default {
+ function = "QSPI0";
+ groups = "QSPI0";
+ };
+
+ pinctrl_spi0_cs1_default: spi0-cs1-default {
+ function = "SPI0CS1";
+ groups = "SPI0CS1";
+ };
+
+ pinctrl_spi1_default: spi1-default {
+ function = "SPI1";
+ groups = "SPI1";
+ };
+
+ pinctrl_spi1_quad_default: spi1-quad-default {
+ function = "QSPI1";
+ groups = "QSPI1";
+ };
+
+ pinctrl_spi1_cs1_default: spi1-cs1-default {
+ function = "SPI1CS1";
+ groups = "SPI1CS1";
+ };
+
+ pinctrl_spi2_default: spi2-default {
+ function = "SPI2";
+ groups = "SPI2";
+ };
+
+ pinctrl_spi2_quad_default: spi2-quad-default {
+ function = "QSPI2";
+ groups = "QSPI2";
+ };
+
+ pinctrl_spi2_cs1_default: spi2-cs1-default {
+ function = "SPI2CS1";
+ groups = "SPI2CS1";
+ };
+
+ pinctrl_espi0_default: espi0-default {
+ function = "ESPI0";
+ groups = "ESPI0";
+ };
+
+ pinctrl_espi1_default: espi1-default {
+ function = "ESPI1";
+ groups = "ESPI1";
+ };
+
+ pinctrl_lpc0_default: lpc0-default {
+ function = "LPC0";
+ groups = "LPC0";
+ };
+
+ pinctrl_lpc1_default: lpc1-default {
+ function = "LPC1";
+ groups = "LPC1";
+ };
+
+ pinctrl_vpi_default: vpi-default {
+ function = "VPI";
+ groups = "VPI";
+ };
+
+ pinctrl_sd_default: sd-default {
+ function = "SD";
+ groups = "SD";
+ };
+
+ pinctrl_hvi3c0_default: hvi3c0-default {
+ function = "I3C0";
+ groups = "HVI3C0";
+ };
+
+ pinctrl_hvi3c1_default: hvi3c1-default {
+ function = "I3C1";
+ groups = "HVI3C1";
+ };
+
+ pinctrl_hvi3c2_default: hvi3c2-default {
+ function = "I3C2";
+ groups = "HVI3C2";
+ };
+
+ pinctrl_hvi3c3_default: hvi3c3-default {
+ function = "I3C3";
+ groups = "HVI3C3";
+ };
+
+ pinctrl_i3c4_default: i3c4-default {
+ function = "I3C4";
+ groups = "I3C4";
+ };
+
+ pinctrl_i3c5_default: i3c5-default {
+ function = "I3C5";
+ groups = "I3C5";
+ };
+
+ pinctrl_i3c6_default: i3c6-default {
+ function = "I3C6";
+ groups = "I3C6";
+ };
+
+ pinctrl_i3c7_default: i3c7-default {
+ function = "I3C7";
+ groups = "I3C7";
+ };
+
+ pinctrl_i3c8_default: i3c8-default {
+ function = "I3C8";
+ groups = "I3C8";
+ };
+
+ pinctrl_i3c9_default: i3c9-default {
+ function = "I3C9";
+ groups = "I3C9";
+ };
+
+ pinctrl_i3c10_default: i3c10-default {
+ function = "I3C10";
+ groups = "I3C10";
+ };
+
+ pinctrl_i3c11_default: i3c11-default {
+ function = "I3C11";
+ groups = "I3C11";
+ };
+
+ pinctrl_hvi3c12_default: hvi3c12-default {
+ function = "I3C12";
+ groups = "HVI3C12";
+ };
+
+ pinctrl_hvi3c13_default: hvi3c13-default {
+ function = "I3C13";
+ groups = "HVI3C13";
+ };
+
+ pinctrl_hvi3c14_default: hvi3c14-default {
+ function = "I3C14";
+ groups = "HVI3C14";
+ };
+
+ pinctrl_hvi3c15_default: hvi3c15-default {
+ function = "I3C15";
+ groups = "HVI3C15";
+ };
+
+ pinctrl_tach0_default: tach0-default {
+ function = "TACH0";
+ groups = "TACH0";
+ };
+
+ pinctrl_tach1_default: tach1-default {
+ function = "TACH1";
+ groups = "TACH1";
+ };
+
+ pinctrl_tach2_default: tach2-default {
+ function = "TACH2";
+ groups = "TACH2";
+ };
+
+ pinctrl_tach3_default: tach3-default {
+ function = "TACH3";
+ groups = "TACH3";
+ };
+
+ pinctrl_tach4_default: tach4-default {
+ function = "TACH4";
+ groups = "TACH4";
+ };
+
+ pinctrl_tach5_default: tach5-default {
+ function = "TACH5";
+ groups = "TACH5";
+ };
+
+ pinctrl_tach6_default: tach6-default {
+ function = "TACH6";
+ groups = "TACH6";
+ };
+
+ pinctrl_tach7_default: tach7-default {
+ function = "TACH7";
+ groups = "TACH7";
+ };
+
+ pinctrl_tach8_default: tach8-default {
+ function = "TACH8";
+ groups = "TACH8";
+ };
+
+ pinctrl_tach9_default: tach9-default {
+ function = "TACH9";
+ groups = "TACH9";
+ };
+
+ pinctrl_tach10_default: tach10-default {
+ function = "TACH10";
+ groups = "TACH10";
+ };
+
+ pinctrl_tach11_default: tach11-default {
+ function = "TACH11";
+ groups = "TACH11";
+ };
+
+ pinctrl_tach12_default: tach12-default {
+ function = "TACH12";
+ groups = "TACH12";
+ };
+
+ pinctrl_tach13_default: tach13-default {
+ function = "TACH13";
+ groups = "TACH13";
+ };
+
+ pinctrl_tach14_default: tach14-default {
+ function = "TACH14";
+ groups = "TACH14";
+ };
+
+ pinctrl_tach15_default: tach15-default {
+ function = "TACH15";
+ groups = "TACH15";
+ };
+
+ pinctrl_thru0_default: thru0-default {
+ function = "THRU0";
+ groups = "THRU0";
+ };
+
+ pinctrl_thru1_default: thru1-default {
+ function = "THRU1";
+ groups = "THRU1";
+ };
+
+ pinctrl_thru2_default: thru2-default {
+ function = "THRU2";
+ groups = "THRU2";
+ };
+
+ pinctrl_thru3_default: thru3-default {
+ function = "THRU3";
+ groups = "THRU3";
+ };
+
+ pinctrl_ncts5_default: ncts5-default {
+ function = "NCTS5";
+ groups = "NCTS5";
+ };
+
+ pinctrl_ndcd5_default: ndcd5-default {
+ function = "NDCD5";
+ groups = "NDCD5";
+ };
+
+ pinctrl_ndsr5_default: ndsr5-default {
+ function = "NDSR5";
+ groups = "NDSR5";
+ };
+
+ pinctrl_nri5_default: nri5-default {
+ function = "NRI5";
+ groups = "NRI5";
+ };
+
+ pinctrl_i2c0_default: i2c0-default {
+ function = "I2C0";
+ groups = "I2C0";
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ function = "I2C1";
+ groups = "I2C1";
+ };
+
+ pinctrl_i2c2_default: i2c2-default {
+ function = "I2C2";
+ groups = "I2C2";
+ };
+
+ pinctrl_i2c3_default: i2c3-default {
+ function = "I2C3";
+ groups = "I2C3";
+ };
+
+ pinctrl_i2c4_default: i2c4-default {
+ function = "I2C4";
+ groups = "I2C4";
+ };
+
+ pinctrl_i2c5_default: i2c5-default {
+ function = "I2C5";
+ groups = "I2C5";
+ };
+
+ pinctrl_i2c6_default: i2c6-default {
+ function = "I2C6";
+ groups = "I2C6";
+ };
+
+ pinctrl_i2c7_default: i2c7-default {
+ function = "I2C7";
+ groups = "I2C7";
+ };
+
+ pinctrl_i2c8_default: i2c8-default {
+ function = "I2C8";
+ groups = "I2C8";
+ };
+
+ pinctrl_i2c9_default: i2c9-default {
+ function = "I2C9";
+ groups = "I2C9";
+ };
+
+ pinctrl_i2c10_default: i2c10-default {
+ function = "I2C10";
+ groups = "I2C10";
+ };
+
+ pinctrl_i2c11_default: i2c11-default {
+ function = "I2C11";
+ groups = "I2C11";
+ };
+
+ pinctrl_i2c12_default: i2c12-default {
+ function = "I2C12";
+ groups = "I2C12";
+ };
+
+ pinctrl_i2c13_default: i2c13-default {
+ function = "I2C13";
+ groups = "I2C13";
+ };
+
+ pinctrl_i2c14_default: i2c14-default {
+ function = "I2C14";
+ groups = "I2C14";
+ };
+
+ pinctrl_i2c15_default: i2c15-default {
+ function = "I2C15";
+ groups = "I2C15";
+ };
+
+ pinctrl_salt0_default: salt0-default {
+ function = "SALT0";
+ groups = "SALT0";
+ };
+
+ pinctrl_salt1_default: salt1-default {
+ function = "SALT1";
+ groups = "SALT1";
+ };
+
+ pinctrl_salt2_default: salt2-default {
+ function = "SALT2";
+ groups = "SALT2";
+ };
+
+ pinctrl_salt3_default: salt3-default {
+ function = "SALT3";
+ groups = "SALT3";
+ };
+
+ pinctrl_salt4_default: salt4-default {
+ function = "SALT4";
+ groups = "SALT4";
+ };
+
+ pinctrl_salt5_default: salt5-default {
+ function = "SALT5";
+ groups = "SALT5";
+ };
+
+ pinctrl_salt6_default: salt6-default {
+ function = "SALT6";
+ groups = "SALT6";
+ };
+
+ pinctrl_salt7_default: salt7-default {
+ function = "SALT7";
+ groups = "SALT7";
+ };
+
+ pinctrl_salt8_default: salt8-default {
+ function = "SALT8";
+ groups = "SALT8";
+ };
+
+ pinctrl_salt9_default: salt9-default {
+ function = "SALT9";
+ groups = "SALT9";
+ };
+
+ pinctrl_salt10_default: salt10-default {
+ function = "SALT10";
+ groups = "SALT10";
+ };
+
+ pinctrl_salt11_default: salt11-default {
+ function = "SALT11";
+ groups = "SALT11";
+ };
+
+ pinctrl_salt12_default: salt12-default {
+ function = "SALT12";
+ groups = "SALT12";
+ };
+
+ pinctrl_salt13_default: salt13-default {
+ function = "SALT13";
+ groups = "SALT13";
+ };
+
+ pinctrl_salt14_default: salt14-default {
+ function = "SALT14";
+ groups = "SALT14";
+ };
+
+ pinctrl_salt15_default: salt15-default {
+ function = "SALT15";
+ groups = "SALT15";
+ };
+
+ pinctrl_can_default: can-default {
+ function = "CANBUS";
+ groups = "CANBUS";
+ };
+ pinctrl_di2c0_default: di2c0-default {
+ function = "I2C0";
+ groups = "DI2C0";
+ };
+
+ pinctrl_di2c1_default: di2c1-default {
+ function = "I2C1";
+ groups = "DI2C1";
+ };
+
+ pinctrl_di2c2_default: di2c2-default {
+ function = "I2C2";
+ groups = "DI2C2";
+ };
+
+ pinctrl_di2c3_default: di2c3-default {
+ function = "I2C3";
+ groups = "DI2C3";
+ };
+ pinctrl_di2c8_default: di2c8-default {
+ function = "I2C8";
+ groups = "DI2C8";
+ };
+
+ pinctrl_di2c9_default: di2c9-default {
+ function = "I2C9";
+ groups = "DI2C9";
+ };
+
+ pinctrl_di2c10_default: di2c10-default {
+ function = "I2C10";
+ groups = "DI2C10";
+ };
+
+ pinctrl_di2c11_default: di2c11-default {
+ function = "I2C11";
+ groups = "DI2C11";
+ };
+
+ pinctrl_di2c12_default: id2c12-default {
+ function = "I2C12";
+ groups = "DI2C12";
+ };
+
+ pinctrl_di2c13_default: di2c13-default {
+ function = "I2C13";
+ groups = "DI2C13";
+ };
+
+ pinctrl_di2c14_default: di2c14-default {
+ function = "I2C14";
+ groups = "DI2C14";
+ };
+
+ pinctrl_di2c15_default: di2c15-default {
+ function = "I2C15";
+ groups = "DI2C15";
+ };
+
+ pinctrl_ncts0_default: ncts0-default {
+ function = "UART0";
+ groups = "NCTS0";
+ };
+
+ pinctrl_ndcd0_default: ndcd0-default {
+ function = "UART0";
+ groups = "NDCD0";
+ };
+
+ pinctrl_ndsr0_default: ndsr0-default {
+ function = "UART0";
+ groups = "NDSR0";
+ };
+
+ pinctrl_nri0_default: nri0-default {
+ function = "UART0";
+ groups = "NRI0";
+ };
+
+ pinctrl_ndtr0_default: ndtr0-default {
+ function = "UART0";
+ groups = "NDTR0";
+ };
+
+ pinctrl_nrts0_default: nrts0-default {
+ function = "UART0";
+ groups = "NRTS0";
+ };
+
+ pinctrl_txd0_default: txd0-default {
+ function = "UART0";
+ groups = "TXD0";
+ };
+
+ pinctrl_rxd0_default: rxd0-default {
+ function = "UART0";
+ groups = "RXD0";
+ };
+
+ pinctrl_ncts1_default: ncts1-default {
+ function = "UART1";
+ groups = "NCTS1";
+ };
+
+ pinctrl_ndcd1_default: ndcd1-default {
+ function = "UART1";
+ groups = "NDCD1";
+ };
+
+ pinctrl_ndsr1_default: ndsr1-default {
+ function = "UART1";
+ groups = "NDSR1";
+ };
+
+ pinctrl_nri1_default: nri1-default {
+ function = "UART1";
+ groups = "NRI1";
+ };
+
+ pinctrl_ndtr1_default: ndtr1-default {
+ function = "UART1";
+ groups = "NDTR1";
+ };
+
+ pinctrl_nrts1_default: nrts1-default {
+ function = "UART1";
+ groups = "NRTS1";
+ };
+
+ pinctrl_txd1_default: txd1-default {
+ function = "UART1";
+ groups = "TXD1";
+ };
+
+ pinctrl_rxd1_default: rxd1-default {
+ function = "UART1";
+ groups = "RXD1";
+ };
+
+ pinctrl_txd2_default: txd2-default {
+ function = "UART2";
+ groups = "TXD2";
+ };
+
+ pinctrl_rxd2_default: rxd2-default {
+ function = "UART2";
+ groups = "RXD2";
+ };
+
+ pinctrl_txd3_default: txd3-default {
+ function = "UART3";
+ groups = "TXD3";
+ };
+
+ pinctrl_rxd3_default: rxd3-default {
+ function = "UART3";
+ groups = "RXD3";
+ };
+
+ pinctrl_ncts5_default: ncts5-default {
+ function = "UART5";
+ groups = "NCTS5";
+ };
+
+ pinctrl_ndcd5_default: ndcd5-default {
+ function = "UART5";
+ groups = "NDCD5";
+ };
+
+ pinctrl_ndsr5_default: ndsr5-default {
+ function = "UART5";
+ groups = "NDSR5";
+ };
+
+ pinctrl_nri5_default: nri5-default {
+ function = "UART5";
+ groups = "NRI5";
+ };
+
+ pinctrl_ndtr5_default: ndtr5-default {
+ function = "UART5";
+ groups = "NDTR5";
+ };
+
+ pinctrl_nrts5_default: nrts5-default {
+ function = "UART5";
+ groups = "NRTS5";
+ };
+
+ pinctrl_txd5_default: txd5-default {
+ function = "UART5";
+ groups = "TXD5";
+ };
+
+ pinctrl_rxd5_default: rxd5-default {
+ function = "UART5";
+ groups = "RXD5";
+ };
+
+ pinctrl_ncts6_default: ncts6-default {
+ function = "UART6";
+ groups = "NCTS6";
+ };
+
+ pinctrl_ndcd6_default: ndcd6-default {
+ function = "UART6";
+ groups = "NDCD6";
+ };
+
+ pinctrl_ndsr6_default: ndsr6-default {
+ function = "UART6";
+ groups = "NDSR6";
+ };
+
+ pinctrl_nri6_default: nri6-default {
+ function = "UART6";
+ groups = "NRI6";
+ };
+
+ pinctrl_ndtr6_default: ndtr6-default {
+ function = "UART6";
+ groups = "NDTR6";
+ };
+
+ pinctrl_nrts6_default: nrts6-default {
+ function = "UART6";
+ groups = "NRTS6";
+ };
+
+ pinctrl_txd6_default: txd6-default {
+ function = "UART6";
+ groups = "TXD6";
+ };
+
+ pinctrl_rxd6_default: rxd6-default {
+ function = "UART6";
+ groups = "RXD6";
+ };
+
+ pinctrl_txd7_default: txd7-default {
+ function = "UART7";
+ groups = "TXD7";
+ };
+
+ pinctrl_rxd7_default: rxd7-default {
+ function = "UART7";
+ groups = "RXD7";
+ };
+
+ pinctrl_txd8_default: txd8-default {
+ function = "UART8";
+ groups = "TXD8";
+ };
+
+ pinctrl_rxd8_default: rxd8-default {
+ function = "UART8";
+ groups = "RXD8";
+ };
+
+ pinctrl_txd9_default: txd9-default {
+ function = "UART9";
+ groups = "TXD9";
+ };
+
+ pinctrl_rxd9_default: rxd9-default {
+ function = "UART9";
+ groups = "RXD9";
+ };
+
+ pinctrl_txd10_default: txd10-default {
+ function = "UART10";
+ groups = "TXD10";
+ };
+
+ pinctrl_rxd10_default: rxd10-default {
+ function = "UART10";
+ groups = "RXD10";
+ };
+
+ pinctrl_txd11_default: txd11-default {
+ function = "UART11";
+ groups = "TXD11";
+ };
+
+ pinctrl_rxd11_default: rxd11-default {
+ function = "UART11";
+ groups = "RXD11";
+ };
+
+ pinctrl_pcierc2_perst_default: pcierc2-perst-default {
+ function = "PCIERC";
+ groups = "PE2SGRSTN";
+ };
+
+ pinctrl_usb2cud_default: usb2cud-default {
+ function = "USB2C";
+ groups = "USB2CUD";
+ };
+
+ pinctrl_usb2cd_default: usb2cd-default {
+ function = "USB2C";
+ groups = "USB2CD";
+ };
+
+ pinctrl_usb2ch_default: usb2ch-default {
+ function = "USB2C";
+ groups = "USB2CH";
+ };
+
+ pinctrl_usb2cu_default: usb2cu-default {
+ function = "USB2C";
+ groups = "USB2CU";
+ };
+
+ pinctrl_usb2dd_default: usb2dd-default {
+ function = "USB2D";
+ groups = "USB2DD";
+ };
+
+ pinctrl_usb2dh_default: usb2dh-default {
+ function = "USB2D";
+ groups = "USB2DH";
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v1 0/4] Add pinctrl support for AST2700 SoC
2025-08-29 7:30 [PATCH v1 0/4] Add pinctrl support for AST2700 SoC Billy Tsai
` (2 preceding siblings ...)
2025-08-29 7:30 ` [PATCH v1 4/4] arm64: dts: add AST27xx pinctrl configuration nodes Billy Tsai
@ 2025-08-29 14:27 ` Rob Herring (Arm)
3 siblings, 0 replies; 7+ messages in thread
From: Rob Herring (Arm) @ 2025-08-29 14:27 UTC (permalink / raw)
To: Billy Tsai
Cc: lee, conor+dt, joel, devicetree, linux-kernel, andrew,
linux-aspeed, krzk+dt, brgl, linux-gpio, linux-arm-kernel,
openbmc, linus.walleij, BMC-SW
On Fri, 29 Aug 2025 15:30:26 +0800, Billy Tsai wrote:
> Document and add the pinctrl driver for AST2700 SoC.
>
> Billy Tsai (4):
> dt-bindings: mfd: aspeed,ast2x00-scu: Support ast2700 pinctrl
> dt-bindings: pinctrl: aspeed: Add support for AST27xx
> pinctrl: aspeed: Add AST2700 pinmux support
> arm64: dts: add AST27xx pinctrl configuration nodes
>
> .../bindings/mfd/aspeed,ast2x00-scu.yaml | 2 +
> .../pinctrl/aspeed,ast2700-soc0-pinctrl.yaml | 135 +
> .../pinctrl/aspeed,ast2700-soc1-pinctrl.yaml | 452 +++
> .../boot/dts/aspeed/aspeed-g7-pinctrl.dtsi | 1359 +++++++++
> drivers/pinctrl/aspeed/Kconfig | 8 +
> drivers/pinctrl/aspeed/Makefile | 1 +
> .../pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c | 503 ++++
> .../pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c | 2523 +++++++++++++++++
> drivers/pinctrl/aspeed/pinctrl-aspeed.c | 47 +
> drivers/pinctrl/aspeed/pinctrl-aspeed.h | 11 +-
> drivers/pinctrl/aspeed/pinmux-aspeed.h | 35 +-
> 11 files changed, 5071 insertions(+), 5 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
> create mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml
> create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7-pinctrl.dtsi
> create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c
> create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c
>
> --
> 2.25.1
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: attempting to guess base-commit...
Base: tags/next-20250828 (exact match)
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/aspeed/' for 20250829073030.2749482-1-billy_tsai@aspeedtech.com:
Traceback (most recent call last):
File "/home/rob/.local/bin/dt-validate", line 8, in <module>
sys.exit(main())
~~~~^^
File "/home/rob/proj/dt-schema/dtschema/dtb_validate.py", line 139, in main
sg = schema_group(args.preparse)
File "/home/rob/proj/dt-schema/dtschema/dtb_validate.py", line 24, in __init__
self.validator = dtschema.DTValidator([schema_file])
~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^
File "/home/rob/proj/dt-schema/dtschema/validator.py", line 376, in __init__
if '$id' in schema_cache:
^^^^^^^^^^^^^^^^^^^^^
TypeError: argument of type 'NoneType' is not iterable
^ permalink raw reply [flat|nested] 7+ messages in thread