From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5F00CA0FF0 for ; Mon, 1 Sep 2025 06:18:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Zb2e1UJDlseKMMev+81jfZOWccINvEhFRYBkYXxN2lY=; b=XDOqgsGoDQQ/UC1vx6+EoHCqfx EpOeWGAxMa8E38rGAEEYjLvrMBCpqmXhfrM5+HHfivqOoC7ctUpy0u/fPbOVEuKlm1TAjosGMLno4 u8TvtBVCVxSsIF8XDjIMFeteYd3CuIyYCUftT/dXwT18OKFaXrc0g3xb0EjLPtJikT1YKOiRN62m0 upNmZa1nARd5GUNW66spD8Hr1N0VjutH4cekOAUyEDj6yti9I2Se5pIDRT7XTSLzuM4FAZ/dkB9WN de7Yw/bKxVvyJoIikbkFDi5CAKTOdrWJl31cR9/RUMnihqKjJgfNmQDKB+zDp8zh+t8p2womsInkM dxaNsJLA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1usxsB-0000000BJI7-07bV; Mon, 01 Sep 2025 06:18:35 +0000 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1usxZh-0000000BGBM-07ST; Mon, 01 Sep 2025 05:59:30 +0000 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 1 Sep 2025 13:59:22 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 1 Sep 2025 13:59:22 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v3 01/10] dt-bindings: soc: aspeed: Add ASPEED PCIe Config Date: Mon, 1 Sep 2025 13:59:13 +0800 Message-ID: <20250901055922.1553550-2-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250901055922.1553550-1-jacky_chou@aspeedtech.com> References: <20250901055922.1553550-1-jacky_chou@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250831_225929_067467_2D5A2D31 X-CRM114-Status: GOOD ( 10.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the ASPEED PCIe configuration syscon block. This shared register space is used by multiple PCIe-related devices to coordinate and manage common PCIe settings. The binding describes the required compatible strings and register space for the configuration node. Signed-off-by: Jacky Chou --- .../soc/aspeed/aspeed,ast2700-pcie-cfg.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/aspeed/aspeed,ast2700-pcie-cfg.yaml diff --git a/Documentation/devicetree/bindings/soc/aspeed/aspeed,ast2700-pcie-cfg.yaml b/Documentation/devicetree/bindings/soc/aspeed/aspeed,ast2700-pcie-cfg.yaml new file mode 100644 index 000000000000..c1a90bb6a785 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/aspeed/aspeed,ast2700-pcie-cfg.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/aspeed/aspeed,ast2700-pcie-cfg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED PCIe Configuration + +maintainers: + - Jacky Chou + +description: + The ASPEED PCIe configuration syscon block provides a set of registers shared + by multiple PCIe-related devices within the SoC. This node represents the + common configuration space that allows these devices to coordinate and manage + shared PCIe settings, including address mapping, control, and status + registers. The syscon interface enables for various PCIe devices to access + and modify these shared registers in a consistent and centralized manner. + +properties: + compatible: + items: + - enum: + - aspeed,ast2700-pcie-cfg + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc0 { + #address-cells = <2>; + #size-cells = <1>; + + syscon@12c02a00 { + compatible = "aspeed,ast2700-pcie-cfg", "syscon"; + reg = <0 0x12c02a00 0x80>; + }; + }; -- 2.43.0