From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 34B03CA1005 for ; Wed, 3 Sep 2025 00:47:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=s4dt/DAxilrmhu9dISzfNpZwds1nWY7gmPX5poCPHmI=; b=WkCZGfVHwzJ4TL5GEOfkQVg8lp OTUwfpGVgB3dyIJSXLqHzjGJNQZXteaBXMzNNPJAsAnBYNjxciSwipkpJt5ZcQCAO0kkn/3wk9KDr u3RjWqFvOKShmtAauE0YpfvuTNEw7UIqdIT0+utBFl/1tfWI0h2XJxTkavIR/IvhHkTiRo23iJ9P2 Kcs7+adw6pxlVfsLoH5NU2DLcEJN+CKdlzG8Pk2VJSDDhr4vnEdtyZK5F43f1fpmiTa4kjky8+r0W LuKh6ZFHo27E576fqg/ub9mCg0KucSdLFod/W0ubFWU2r40o8Jcm/iC78WL2UHqH8m4Gb3y3/91RG 5ug3P5HA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1utbev-00000002twA-1AFX; Wed, 03 Sep 2025 00:47:33 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1utb4P-00000002iy6-2LOc for linux-arm-kernel@lists.infradead.org; Wed, 03 Sep 2025 00:09:50 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A7548176A; Tue, 2 Sep 2025 17:09:40 -0700 (PDT) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 411363F63F; Tue, 2 Sep 2025 17:09:47 -0700 (PDT) From: Andre Przywara To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jernej Skrabec , Chen-Yu Tsai , Samuel Holland Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Mikhail Kalashnikov Subject: [PATCH 5/5] arm64: dts: allwinner: a523: add CPU clocks Date: Wed, 3 Sep 2025 01:09:10 +0100 Message-ID: <20250903000910.4860-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250903000910.4860-1-andre.przywara@arm.com> References: <20250903000910.4860-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250902_170949_711656_EB149717 X-CRM114-Status: GOOD ( 12.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Allwinner A523 family of SoCs feature a separate clock unit for the CPU PLLs and muxes, including one for the DSU interconnect. Add a DT node for the CPU clock controller, and list all the clocks from the other CCUs that this controller needs. Also list the clock source for each CPU: there is one clock for each cluster of four cores, suffixed L and B, for little and big (although all cores are of the same Cortex-A55 type). Signed-off-by: Andre Przywara --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index 6b6f2296bdff6..98a59d324bfeb 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,7 @@ cpu0: cpu@0 { device_type = "cpu"; reg = <0x000>; enable-method = "psci"; + clocks = <&cpu_ccu CLK_CPU_L>; }; cpu1: cpu@100 { @@ -31,6 +33,7 @@ cpu1: cpu@100 { device_type = "cpu"; reg = <0x100>; enable-method = "psci"; + clocks = <&cpu_ccu CLK_CPU_L>; }; cpu2: cpu@200 { @@ -38,6 +41,7 @@ cpu2: cpu@200 { device_type = "cpu"; reg = <0x200>; enable-method = "psci"; + clocks = <&cpu_ccu CLK_CPU_L>; }; cpu3: cpu@300 { @@ -45,6 +49,7 @@ cpu3: cpu@300 { device_type = "cpu"; reg = <0x300>; enable-method = "psci"; + clocks = <&cpu_ccu CLK_CPU_L>; }; cpu4: cpu@400 { @@ -52,6 +57,7 @@ cpu4: cpu@400 { device_type = "cpu"; reg = <0x400>; enable-method = "psci"; + clocks = <&cpu_ccu CLK_CPU_B>; }; cpu5: cpu@500 { @@ -59,6 +65,7 @@ cpu5: cpu@500 { device_type = "cpu"; reg = <0x500>; enable-method = "psci"; + clocks = <&cpu_ccu CLK_CPU_B>; }; cpu6: cpu@600 { @@ -66,6 +73,7 @@ cpu6: cpu@600 { device_type = "cpu"; reg = <0x600>; enable-method = "psci"; + clocks = <&cpu_ccu CLK_CPU_B>; }; cpu7: cpu@700 { @@ -73,6 +81,7 @@ cpu7: cpu@700 { device_type = "cpu"; reg = <0x700>; enable-method = "psci"; + clocks = <&cpu_ccu CLK_CPU_B>; }; }; @@ -690,5 +699,18 @@ rtc: rtc@7090000 { clock-names = "bus", "hosc", "ahb"; #clock-cells = <1>; }; + + cpu_ccu: clock-controller@8817000 { + compatible = "allwinner,sun55i-a523-cpu-ccu"; + reg = <0x08817000 0x80>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0_2X>, + <&ccu CLK_PLL_PERIPH0_600M>; + clock-names = "hosc", "losc", + "iosc", "pll-periph0-2x", + "pll-periph0-600M"; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; }; -- 2.46.3